Add ucb-art/chisel-jtag (#612)
* jtag: Add ucb-art/chisel-jtag to junctions. * jtag: Add missing Utils file for Tristate and NegativeEdgeLatch * jtag: move to a top-level package
This commit is contained in:
Megan Wachs
GitHub
parent
0e2b780089
commit
8e6beb80be
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chisel-jtag license terms
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Copyright (c) 2016 The Regents of the University of
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California (Regents). All Rights Reserved. Redistribution and use in
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source and binary forms, with or without modification, are permitted
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provided that the following conditions are met:
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* Redistributions of source code must retain the above
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copyright notice, this list of conditions and the following
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two paragraphs of disclaimer.
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* Redistributions in binary form must reproduce the above
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copyright notice, this list of conditions and the following
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two paragraphs of disclaimer in the documentation and/or other materials
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provided with the distribution.
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* Neither the name of the Regents nor the names of its contributors
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may be used to endorse or promote products derived from this
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software without specific prior written permission.
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IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
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SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
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ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
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REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF
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ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION
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TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
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MODIFICATIONS.
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// See LICENSE.jtag for license details.
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package jtag
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import chisel3._
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import chisel3.core.DataMirror
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import chisel3.internal.firrtl.KnownWidth
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import chisel3.util._
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/** Base JTAG shifter IO, viewed from input to shift register chain.
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* Can be chained together.
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*/
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class ShifterIO extends Bundle {
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val shift = Bool() // advance the scan chain on clock high
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val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB
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val capture = Bool() // high in the CaptureIR/DR state when this chain is selected
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val update = Bool() // high in the UpdateIR/DR state when this chain is selected
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/** Sets a output shifter IO's control signals from a input shifter IO's control signals.
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*/
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def chainControlFrom(in: ShifterIO) {
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shift := in.shift
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capture := in.capture
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update := in.update
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}
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}
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trait ChainIO extends Bundle {
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val chainIn = Input(new ShifterIO)
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val chainOut = Output(new ShifterIO)
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}
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class Capture[+T <: Data](gen: T) extends Bundle {
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val bits = Input(gen) // data to capture, should be always valid
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val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge
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override def cloneType = Capture(gen).asInstanceOf[this.type]
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}
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object Capture {
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def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)
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}
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/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain
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* IO.
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*/
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trait Chain extends Module {
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val io: ChainIO
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}
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/** One-element shift register, data register for bypass mode.
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*
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* Implements Clause 10.
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*/
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class JtagBypassChain extends Chain {
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class ModIO extends ChainIO
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val io = IO(new ModIO)
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io.chainOut chainControlFrom io.chainIn
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val reg = Reg(Bool()) // 10.1.1a single shift register stage
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io.chainOut.data := reg
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when (io.chainIn.capture) {
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reg := false.B // 10.1.1b capture logic 0 on TCK rising
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} .elsewhen (io.chainIn.shift) {
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reg := io.chainIn.data
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}
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assert(!(io.chainIn.capture && io.chainIn.update)
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&& !(io.chainIn.capture && io.chainIn.shift)
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&& !(io.chainIn.update && io.chainIn.shift))
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}
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object JtagBypassChain {
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def apply() = new JtagBypassChain
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}
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/** Simple shift register with parallel capture only, for read-only data registers.
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*
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* Number of stages is the number of bits in gen, which must have a known width.
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*
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* Useful notes:
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* 7.2.1c shifter shifts on TCK rising edge
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* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
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*/
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class CaptureChain[+T <: Data](gen: T) extends Chain {
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class ModIO extends ChainIO {
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val capture = Capture(gen)
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}
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val io = IO(new ModIO)
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io.chainOut chainControlFrom io.chainIn
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val n = DataMirror.widthOf(gen) match {
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case KnownWidth(x) => x
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case _ => require(false, s"can't generate chain for unknown width data type $gen"); -1 // TODO: remove -1 type hack
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}
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val regs = (0 until n) map (x => Reg(Bool()))
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io.chainOut.data := regs(0)
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when (io.chainIn.capture) {
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(0 until n) map (x => regs(x) := io.capture.bits.asUInt()(x))
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io.capture.capture := true.B
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} .elsewhen (io.chainIn.shift) {
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regs(n-1) := io.chainIn.data
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(0 until n-1) map (x => regs(x) := regs(x+1))
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io.capture.capture := false.B
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} .otherwise {
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io.capture.capture := false.B
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}
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assert(!(io.chainIn.capture && io.chainIn.update)
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&& !(io.chainIn.capture && io.chainIn.shift)
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&& !(io.chainIn.update && io.chainIn.shift))
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}
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object CaptureChain {
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def apply[T <: Data](gen: T) = new CaptureChain(gen)
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}
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/** Simple shift register with parallel capture and update. Useful for general instruction and data
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* scan registers.
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*
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* Number of stages is the max number of bits in genCapture and genUpdate, both of which must have
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* known widths. If there is a width mismatch, the unused most significant bits will be zero.
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*
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* Useful notes:
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* 7.2.1c shifter shifts on TCK rising edge
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* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
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*/
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class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V) extends Chain {
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class ModIO extends ChainIO {
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val capture = Capture(genCapture)
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val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after
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}
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val io = IO(new ModIO)
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io.chainOut chainControlFrom io.chainIn
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val captureWidth = DataMirror.widthOf(genCapture) match {
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case KnownWidth(x) => x
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case _ => require(false, s"can't generate chain for unknown width data type $genCapture"); -1 // TODO: remove -1 type hack
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}
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val updateWidth = DataMirror.widthOf(genUpdate) match {
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case KnownWidth(x) => x
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case _ => require(false, s"can't generate chain for unknown width data type $genUpdate"); -1 // TODO: remove -1 type hack
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}
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val n = math.max(captureWidth, updateWidth)
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val regs = (0 until n) map (x => Reg(Bool()))
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io.chainOut.data := regs(0)
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val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
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io.update.bits := io.update.bits.fromBits(updateBits)
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val captureBits = io.capture.bits.asUInt()
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when (io.chainIn.capture) {
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(0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))
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(captureWidth until n) map (x => regs(x) := 0.U)
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io.capture.capture := true.B
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io.update.valid := false.B
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} .elsewhen (io.chainIn.update) {
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io.capture.capture := false.B
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io.update.valid := true.B
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} .elsewhen (io.chainIn.shift) {
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regs(n-1) := io.chainIn.data
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(0 until n-1) map (x => regs(x) := regs(x+1))
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io.capture.capture := false.B
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io.update.valid := false.B
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} .otherwise {
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io.capture.capture := false.B
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io.update.valid := false.B
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}
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assert(!(io.chainIn.capture && io.chainIn.update)
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&& !(io.chainIn.capture && io.chainIn.shift)
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&& !(io.chainIn.update && io.chainIn.shift))
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}
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object CaptureUpdateChain {
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/** Capture-update chain with matching capture and update types.
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*/
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def apply[T <: Data](gen: T) = new CaptureUpdateChain(gen, gen)
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def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V) =
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new CaptureUpdateChain(genCapture, genUpdate)
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}
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// See LICENSE.jtag for license details.
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package jtag
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import util.{AsyncResetRegVec}
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import chisel3._
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import chisel3.util._
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object JtagState {
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sealed abstract class State(val id: Int) {
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def U: UInt = id.U(State.width.W)
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}
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object State {
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import scala.language.implicitConversions
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implicit def toInt(x: State) = x.id
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implicit def toBigInt(x: State):BigInt = x.id
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// TODO: this could be automatically generated with macros and stuff
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val all: Set[State] = Set(
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TestLogicReset,
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RunTestIdle,
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SelectDRScan,
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CaptureDR,
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ShiftDR,
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Exit1DR,
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PauseDR,
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Exit2DR,
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UpdateDR,
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SelectIRScan,
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CaptureIR,
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ShiftIR,
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Exit1IR,
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PauseIR,
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Exit2IR,
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UpdateIR
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)
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val width = log2Up(all.size)
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def chiselType() = UInt(width.W)
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}
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// States as described in 6.1.1.2, numeric assignments from example in Table 6-3
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case object TestLogicReset extends State(15) // no effect on system logic, entered when TMS high for 5 TCK rising edges
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case object RunTestIdle extends State(12) // runs active instruction (which can be idle)
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case object SelectDRScan extends State(7)
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case object CaptureDR extends State(6) // parallel-load DR shifter when exiting this state (if required)
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case object ShiftDR extends State(2) // shifts DR shifter from TDI towards TDO, last shift occurs on rising edge transition out of this state
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case object Exit1DR extends State(1)
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case object PauseDR extends State(3) // pause DR shifting
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case object Exit2DR extends State(0)
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case object UpdateDR extends State(5) // parallel-load output from DR shifter on TCK falling edge while in this state (not a rule?)
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case object SelectIRScan extends State(4)
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case object CaptureIR extends State(14) // parallel-load IR shifter with fixed logic values and design-specific when exiting this state (if required)
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case object ShiftIR extends State(10) // shifts IR shifter from TDI towards TDO, last shift occurs on rising edge transition out of this state
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case object Exit1IR extends State(9)
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case object PauseIR extends State(11) // pause IR shifting
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case object Exit2IR extends State(8)
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case object UpdateIR extends State(13) // latch IR shifter into IR (changes to IR may only occur while in this state, latch on TCK falling edge)
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}
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/** The JTAG state machine, implements spec 6.1.1.1a (Figure 6.1)
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*
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* Usage notes:
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* - 6.1.1.1b state transitions occur on TCK rising edge
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* - 6.1.1.1c actions can occur on the following TCK falling or rising edge
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*
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*
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*/
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class JtagStateMachine extends Module(override_reset=Some(false.B)) {
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class StateMachineIO extends Bundle {
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val tms = Input(Bool())
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val currState = Output(JtagState.State.chiselType())
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val jtag_reset = Input(Bool())
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}
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val io = IO(new StateMachineIO)
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val nextState = Wire(JtagState.State.chiselType())
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val currStateReg = Module (new AsyncResetRegVec(w = JtagState.State.width,
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init = JtagState.State.toInt(JtagState.TestLogicReset)))
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currStateReg.clock := clock
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currStateReg.reset := io.jtag_reset
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currStateReg.io.en := true.B
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currStateReg.io.d := nextState
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val currState = currStateReg.io.q
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switch (currState) {
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is (JtagState.TestLogicReset.U) {
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nextState := Mux(io.tms, JtagState.TestLogicReset.U, JtagState.RunTestIdle.U)
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}
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is (JtagState.RunTestIdle.U) {
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nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)
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}
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is (JtagState.SelectDRScan.U) {
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nextState := Mux(io.tms, JtagState.SelectIRScan.U, JtagState.CaptureDR.U)
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}
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is (JtagState.CaptureDR.U) {
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nextState := Mux(io.tms, JtagState.Exit1DR.U, JtagState.ShiftDR.U)
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}
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is (JtagState.ShiftDR.U) {
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nextState := Mux(io.tms, JtagState.Exit1DR.U, JtagState.ShiftDR.U)
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}
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is (JtagState.Exit1DR.U) {
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nextState := Mux(io.tms, JtagState.UpdateDR.U, JtagState.PauseDR.U)
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}
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is (JtagState.PauseDR.U) {
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nextState := Mux(io.tms, JtagState.Exit2DR.U, JtagState.PauseDR.U)
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}
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is (JtagState.Exit2DR.U) {
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nextState := Mux(io.tms, JtagState.UpdateDR.U, JtagState.ShiftDR.U)
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}
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is (JtagState.UpdateDR.U) {
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nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)
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}
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is (JtagState.SelectIRScan.U) {
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nextState := Mux(io.tms, JtagState.TestLogicReset.U, JtagState.CaptureIR.U)
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}
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is (JtagState.CaptureIR.U) {
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nextState := Mux(io.tms, JtagState.Exit1IR.U, JtagState.ShiftIR.U)
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}
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is (JtagState.ShiftIR.U) {
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nextState := Mux(io.tms, JtagState.Exit1IR.U, JtagState.ShiftIR.U)
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}
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is (JtagState.Exit1IR.U) {
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nextState := Mux(io.tms, JtagState.UpdateIR.U, JtagState.PauseIR.U)
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}
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is (JtagState.PauseIR.U) {
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nextState := Mux(io.tms, JtagState.Exit2IR.U, JtagState.PauseIR.U)
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}
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is (JtagState.Exit2IR.U) {
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nextState := Mux(io.tms, JtagState.UpdateIR.U, JtagState.ShiftIR.U)
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}
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is (JtagState.UpdateIR.U) {
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nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)
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}
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}
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io.currState := currState
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}
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@ -0,0 +1,241 @@
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// See LICENSE.jtag for license details.
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package jtag
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import chisel3._
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import chisel3.util._
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/** JTAG signals, viewed from the master side
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*/
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class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
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val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None
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val TCK = Clock(OUTPUT)
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val TMS = Output(Bool())
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val TDI = Output(Bool())
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val TDO = Input(new Tristate())
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override def cloneType = new JTAGIO(hasTRSTn).asInstanceOf[this.type]
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}
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/** JTAG block output signals.
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*/
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class JtagOutput(irLength: Int) extends Bundle {
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val state = Output(JtagState.State.chiselType()) // state, transitions on TCK rising edge
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val instruction = Output(UInt(irLength.W)) // current active instruction
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val reset = Output(Bool()) // synchronous reset asserted in Test-Logic-Reset state, should NOT hold the FSM in reset
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override def cloneType = new JtagOutput(irLength).asInstanceOf[this.type]
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}
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class JtagControl extends Bundle {
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val jtag_reset = Input(Bool())
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}
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/** Aggregate JTAG block IO.
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*/
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class JtagBlockIO(irLength: Int) extends Bundle {
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val jtag = Flipped(new JTAGIO())
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val control = new JtagControl
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val output = new JtagOutput(irLength)
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override def cloneType = new JtagBlockIO(irLength).asInstanceOf[this.type]
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}
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/** Internal controller block IO with data shift outputs.
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*/
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class JtagControllerIO(irLength: Int) extends JtagBlockIO(irLength) {
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val dataChainOut = Output(new ShifterIO)
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val dataChainIn = Input(new ShifterIO)
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override def cloneType = new JtagControllerIO(irLength).asInstanceOf[this.type]
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}
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/** JTAG TAP controller internal block, responsible for instruction decode and data register chain
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* control signal generation.
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*
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* Misc notes:
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* - Figure 6-3 and 6-4 provides examples with timing behavior
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*/
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class JtagTapController(irLength: Int, initialInstruction: BigInt) extends Module {
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require(irLength >= 2) // 7.1.1a
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val io = IO(new JtagControllerIO(irLength))
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val tdo = Wire(Bool()) // 4.4.1c TDI should appear here uninverted after shifting
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val tdo_driven = Wire(Bool())
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io.jtag.TDO.data := NegativeEdgeLatch(clock, tdo, name = Some("tdoReg")) // 4.5.1a TDO changes on falling edge of TCK, 6.1.2.1d driver active on first TCK falling edge in ShiftIR and ShiftDR states
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io.jtag.TDO.driven := NegativeEdgeLatch(clock, tdo_driven, name = Some("tdoeReg"))
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//
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// JTAG state machine
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//
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val stateMachine = Module(new JtagStateMachine)
|
||||
stateMachine.io.tms := io.jtag.TMS
|
||||
val currState = stateMachine.io.currState
|
||||
io.output.state := stateMachine.io.currState
|
||||
|
||||
// At this point, the TRSTn should already have been
|
||||
// combined with any POR, and it should also be
|
||||
// synchronized to TCK.
|
||||
require(!io.jtag.TRSTn.isDefined, "TRSTn should be absorbed into jtckPOReset outside of JtagTapController.")
|
||||
stateMachine.io.jtag_reset := io.control.jtag_reset
|
||||
|
||||
//
|
||||
// Instruction Register
|
||||
//
|
||||
// 7.1.1d IR shifter two LSBs must be b01 pattern
|
||||
// TODO: 7.1.1d allow design-specific IR bits, 7.1.1e (rec) should be a fixed pattern
|
||||
// 7.2.1a behavior of instruction register and shifters
|
||||
val irChain = Module(CaptureUpdateChain(UInt(irLength.W)))
|
||||
irChain.suggestName("irChain")
|
||||
irChain.io.chainIn.shift := currState === JtagState.ShiftIR.U
|
||||
irChain.io.chainIn.data := io.jtag.TDI
|
||||
irChain.io.chainIn.capture := currState === JtagState.CaptureIR.U
|
||||
irChain.io.chainIn.update := currState === JtagState.UpdateIR.U
|
||||
irChain.io.capture.bits := "b01".U
|
||||
|
||||
val updateInstruction = Wire(Bool())
|
||||
|
||||
val nextActiveInstruction = Wire(UInt(irLength.W))
|
||||
val activeInstruction = NegativeEdgeLatch(clock, nextActiveInstruction, updateInstruction, name = Some("irReg")) // 7.2.1d active instruction output latches on TCK falling edge
|
||||
|
||||
when (reset) {
|
||||
nextActiveInstruction := initialInstruction.U(irLength.W)
|
||||
updateInstruction := true.B
|
||||
} .elsewhen (currState === JtagState.UpdateIR.U) {
|
||||
nextActiveInstruction := irChain.io.update.bits
|
||||
updateInstruction := true.B
|
||||
} .otherwise {
|
||||
updateInstruction := false.B
|
||||
}
|
||||
io.output.instruction := activeInstruction
|
||||
|
||||
io.output.reset := currState === JtagState.TestLogicReset.U
|
||||
|
||||
//
|
||||
// Data Register
|
||||
//
|
||||
io.dataChainOut.shift := currState === JtagState.ShiftDR.U
|
||||
io.dataChainOut.data := io.jtag.TDI
|
||||
io.dataChainOut.capture := currState === JtagState.CaptureDR.U
|
||||
io.dataChainOut.update := currState === JtagState.UpdateDR.U
|
||||
|
||||
//
|
||||
// Output Control
|
||||
//
|
||||
when (currState === JtagState.ShiftDR.U) {
|
||||
tdo := io.dataChainIn.data
|
||||
tdo_driven := true.B
|
||||
} .elsewhen (currState === JtagState.ShiftIR.U) {
|
||||
tdo := irChain.io.chainOut.data
|
||||
tdo_driven := true.B
|
||||
} .otherwise {
|
||||
tdo_driven := false.B
|
||||
}
|
||||
}
|
||||
|
||||
object JtagTapGenerator {
|
||||
/** JTAG TAP generator, enclosed module must be clocked from TCK and reset from output of this
|
||||
* block.
|
||||
*
|
||||
* @param irLength length, in bits, of instruction register, must be at least 2
|
||||
* @param instructions map of instruction codes to data register chains that select that data
|
||||
* register; multiple instructions may map to the same data chain
|
||||
* @param idcode optional idcode, tuple of (instruction code, idcode)
|
||||
*
|
||||
* @note all other instruction codes (not part of instructions or idcode) map to BYPASS
|
||||
* @note initial instruction is idcode (if supported), otherwise all ones BYPASS
|
||||
*
|
||||
* Usage notes:
|
||||
* - 4.3.1b TMS must appear high when undriven
|
||||
* - 4.3.1c (rec) minimize load presented by TMS
|
||||
* - 4.4.1b TDI must appear high when undriven
|
||||
* - 4.5.1b TDO must be inactive except when shifting data (undriven? 6.1.2)
|
||||
* - 6.1.3.1b TAP controller must not be (re-?)initialized by system reset (allows
|
||||
* boundary-scan testing of reset pin)
|
||||
* - 6.1 TAP controller can be initialized by a on-chip power on reset generator, the same one
|
||||
* that would initialize system logic
|
||||
*
|
||||
* TODO:
|
||||
* - support concatenated scan chains
|
||||
*/
|
||||
def apply(irLength: Int, instructions: Map[BigInt, Chain], idcode:Option[(BigInt, BigInt)]=None): JtagBlockIO = {
|
||||
// Create IDCODE chain if needed
|
||||
val allInstructions = idcode match {
|
||||
case Some((icode, idcode)) => {
|
||||
val idcodeChain = Module(CaptureChain(UInt(32.W)))
|
||||
idcodeChain.suggestName("idcodeChain")
|
||||
require(idcode % 2 == 1, "LSB must be set in IDCODE, see 12.1.1d")
|
||||
require(((idcode >> 1) & ((1 << 11) - 1)) != JtagIdcode.dummyMfrId, "IDCODE must not have 0b00001111111 as manufacturer identity, see 12.2.1b")
|
||||
require(!(instructions contains icode), "instructions may not contain IDCODE")
|
||||
idcodeChain.io.capture.bits := idcode.U(32.W)
|
||||
instructions + (icode -> idcodeChain)
|
||||
} case None => instructions
|
||||
}
|
||||
|
||||
val bypassIcode = (BigInt(1) << irLength) - 1 // required BYPASS instruction
|
||||
val initialInstruction = idcode match { // 7.2.1e load IDCODE or BYPASS instruction after entry into TestLogicReset
|
||||
case Some((icode, _)) => icode
|
||||
case None => bypassIcode
|
||||
}
|
||||
|
||||
require(!(allInstructions contains bypassIcode), "instructions may not contain BYPASS code")
|
||||
|
||||
val controllerInternal = Module(new JtagTapController(irLength, initialInstruction))
|
||||
|
||||
val unusedChainOut = Wire(new ShifterIO) // De-selected chain output
|
||||
unusedChainOut.shift := false.B
|
||||
unusedChainOut.data := false.B
|
||||
unusedChainOut.capture := false.B
|
||||
unusedChainOut.update := false.B
|
||||
|
||||
val bypassChain = Module(JtagBypassChain())
|
||||
|
||||
// The Great Data Register Chain Mux
|
||||
bypassChain.io.chainIn := controllerInternal.io.dataChainOut // for simplicity, doesn't visibly affect anything else
|
||||
require(allInstructions.size > 0, "Seriously? JTAG TAP with no instructions?")
|
||||
|
||||
val chainToIcode = allInstructions groupBy { case (icode, chain) => chain } map {
|
||||
case (chain, icodeToChain) => chain -> icodeToChain.keys
|
||||
}
|
||||
|
||||
val chainToSelect = chainToIcode map {
|
||||
case (chain, icodes) => {
|
||||
assume(icodes.size > 0)
|
||||
val icodeSelects = icodes map { controllerInternal.io.output.instruction === _.asUInt(irLength.W) }
|
||||
chain -> icodeSelects.reduceLeft(_||_)
|
||||
}
|
||||
}
|
||||
|
||||
def foldOutSelect(res: WhenContext, x: (Chain, Bool)): WhenContext = {
|
||||
val (chain, select) = x
|
||||
// Continue the WhenContext with if this chain is selected
|
||||
res.elsewhen(select) {
|
||||
controllerInternal.io.dataChainIn := chain.io.chainOut
|
||||
}
|
||||
}
|
||||
|
||||
val emptyWhen = when (false.B) { } // Empty WhenContext to start things off
|
||||
chainToSelect.toSeq.foldLeft(emptyWhen)(foldOutSelect).otherwise {
|
||||
controllerInternal.io.dataChainIn := bypassChain.io.chainOut
|
||||
}
|
||||
|
||||
def mapInSelect(x: (Chain, Bool)) {
|
||||
val (chain, select) = x
|
||||
when (select) {
|
||||
chain.io.chainIn := controllerInternal.io.dataChainOut
|
||||
} .otherwise {
|
||||
chain.io.chainIn := unusedChainOut
|
||||
}
|
||||
}
|
||||
|
||||
chainToSelect.map(mapInSelect)
|
||||
|
||||
val internalIo = Wire(new JtagBlockIO(irLength))
|
||||
|
||||
controllerInternal.io.jtag <> internalIo.jtag
|
||||
controllerInternal.io.control <> internalIo.control
|
||||
controllerInternal.io.output <> internalIo.output
|
||||
|
||||
internalIo
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
// See LICENSE.jtag for license details.
|
||||
|
||||
package jtag
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
object JtagIdcode {
|
||||
/** Generates a JTAG IDCODE as a 32-bit integer, using the format in 12.1.1d.
|
||||
*/
|
||||
def apply(version: Int, partNumber: Int, mfrId: Int): BigInt = {
|
||||
require(version < (1 << 4), "version field must be 4 bits at most")
|
||||
require(partNumber < (1 << 16), "part number must be 16 bits at most")
|
||||
require(mfrId < (1 << 11), "manufacturer identity must be 11 bits at most")
|
||||
BigInt(version) << 28 | BigInt(partNumber) << 12 | BigInt(mfrId) << 1 | 1
|
||||
}
|
||||
|
||||
/** A dummy manufacturer ID, not to be used per 12.2.1b since bus masters may shift this out to
|
||||
* determine the end of a bus.
|
||||
*/
|
||||
def dummyMfrId: Int = 0x7f
|
||||
}
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
// See LICENSE.jtag for license details.
|
||||
|
||||
package jtag
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
/** Bundle representing a tristate pin.
|
||||
*/
|
||||
class Tristate extends Bundle {
|
||||
val data = Bool()
|
||||
val driven = Bool() // active high, pin is hi-Z when driven is low
|
||||
}
|
||||
|
||||
class NegativeEdgeLatch[T <: Data](clock: Clock, dataType: T)
|
||||
extends Module(override_clock=Some(clock)) {
|
||||
class IoClass extends Bundle {
|
||||
val next = Input(dataType)
|
||||
val enable = Input(Bool())
|
||||
val output = Output(dataType)
|
||||
}
|
||||
val io = IO(new IoClass)
|
||||
|
||||
val reg = Reg(dataType)
|
||||
when (io.enable) {
|
||||
reg := io.next
|
||||
}
|
||||
io.output := reg
|
||||
}
|
||||
|
||||
/** Generates a register that updates on the falling edge of the input clock signal.
|
||||
*/
|
||||
object NegativeEdgeLatch {
|
||||
def apply[T <: Data](clock: Clock, next: T, enable: Bool=true.B, name: Option[String] = None): T = {
|
||||
// TODO better init passing once in-module multiclock support improves
|
||||
val latch_module = Module(new NegativeEdgeLatch((!clock.asUInt).asClock, next.cloneType))
|
||||
name.foreach(latch_module.suggestName(_))
|
||||
latch_module.io.next := next
|
||||
latch_module.io.enable := enable
|
||||
latch_module.io.output
|
||||
}
|
||||
}
|
||||
|
||||
/** A module that counts transitions on the input clock line, used as a basic sanity check and
|
||||
* debug indicator clock-crossing designs.
|
||||
*/
|
||||
class ClockedCounter(modClock: Clock, counts: BigInt, init: Option[BigInt])
|
||||
extends Module(override_clock=Some(modClock)) {
|
||||
require(counts > 0, "really?")
|
||||
|
||||
val width = log2Up(counts)
|
||||
class CountIO extends Bundle {
|
||||
val count = Output(UInt(width.W))
|
||||
}
|
||||
val io = IO(new CountIO)
|
||||
|
||||
val count = init match {
|
||||
case Some(init) => Reg(UInt(width.W), init=init.U)
|
||||
case None => Reg(UInt(width.W))
|
||||
}
|
||||
|
||||
when (count === (counts - 1).asUInt) {
|
||||
count := 0.U
|
||||
} .otherwise {
|
||||
count := count + 1.U
|
||||
}
|
||||
|
||||
io.count := count
|
||||
}
|
||||
|
||||
/** Count transitions on the input bit by specifying it as a clock to a counter.
|
||||
*/
|
||||
object ClockedCounter {
|
||||
def apply (data: Bool, counts: BigInt, init: BigInt): UInt = {
|
||||
val counter = Module(new ClockedCounter(data.asClock, counts, Some(init)))
|
||||
counter.io.count
|
||||
}
|
||||
def apply (data: Bool, counts: BigInt): UInt = {
|
||||
val counter = Module(new ClockedCounter(data.asClock, counts, None))
|
||||
counter.io.count
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
// See LICENSE.jtag for license details
|
||||
|
||||
import scala.language.implicitConversions
|
||||
|
||||
package object jtag {
|
||||
/** An implicit conversion to allow the instruction map for the TAP generator to be specified as
|
||||
* an Int instead of BigInt. Scala doesn't seem to want to automatically apply the built-in Int
|
||||
* to BigInt conversion when used as a Map key.
|
||||
*
|
||||
* This is limited to value types of Chain to limit application scope.
|
||||
*/
|
||||
implicit def instructionIntKeyToBigInt[V <: Chain](x: (Int, V)) = (BigInt(x._1), x._2)
|
||||
}
|
||||
Loading…
Reference in New Issue