riscv/rocket-chip
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Do some CSE by hand, per @terpstra

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Andrew Waterman 2017-04-10 18:40:49 -07:00 committed by Andrew Waterman
parent 71bf929505
commit 470c6711a7
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/CSR.scala
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@ -479,7 +479,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val base = Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec)
val baseAlign = 2
val interruptAlign = log2Ceil(new MIP().getWidth)
val interruptOffset = cause(log2Ceil(new MIP().getWidth)-1, 0) << baseAlign
val interruptOffset = cause(interruptAlign-1, 0) << baseAlign
val interruptVec = Cat(base >> (interruptAlign + baseAlign), interruptOffset)
Mux(base(0) && cause(cause.getWidth-1), interruptVec, base)
}