riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao 82bbbf908d Fix L2 Writeback deadlock issue 
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.

The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.

The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
 2016-07-26 12:31:08 -07:00
Howard Mao 9168f35971 clean up the requirements in StatelessBridge 
* No need to check that release ID bits and acquire ID bits the same
 * Check that inner and outer coherence policies match
 2016-07-21 19:41:56 -07:00
Howard Mao 12067a3b8d make sure outer probe and finish lines are disconnected 2016-07-21 15:15:44 -07:00
Howard Mao c38dff0855 add some more warnings about the StatelessBridge 2016-07-21 15:07:10 -07:00
Howard Mao 0a1cd64786 fix number of builtin Acquire types 2016-07-21 13:45:20 -07:00
Howard Mao 86e31be820 fix lockup from back to back releases with data 2016-07-21 12:06:58 -07:00
Howard Mao 9eeb1112d4 fix Bufferless irel_vs_iacq_conflict signal 2016-07-18 17:38:20 -07:00
Howard Mao e5cccc0526 don't update xact_vol_irel if not a voluntary irel 2016-07-18 17:05:23 -07:00
Howard Mao 84098db81f add a TileLinkTestRAM 2016-07-15 11:03:26 -07:00
Howard Mao b122a54c32 don't allow more outer IDs than inner IDs 2016-07-13 12:42:28 -07:00
Howard Mao de1e25f3d1 reduce usage of CAMs in converters 2016-07-13 11:20:50 -07:00
Howard Mao 8aa73915a1 put locking arbiter back into converter 2016-07-08 09:31:33 -07:00
Howard Mao a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" 
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.

Conflicts:
	src/main/scala/converters/Nasti.scala
 2016-07-08 09:31:33 -07:00
Howard Mao 16a6b11081 fix bug in AXI -> TL converter 2016-07-07 14:34:24 -07:00
Howard Mao 7cc64011fb simplify amo_mask generation 2016-07-07 12:14:45 -07:00
Howard Mao 1c5e7be75b make sure Nasti write channel id is set correctly 2016-07-07 12:14:02 -07:00
Howard Mao 8ccc50a8f0 fix IdMapper and TL -> NASTI converter 2016-07-07 10:16:44 -07:00
Howard Mao 5d8d5e598b add buffering and locking to TL -> Nasti converter 2016-07-06 16:51:45 -07:00
Howard Mao b10d306b4a add option to log L2 cache transactions for easier debugging 2016-07-06 14:59:09 -07:00
Howard Mao 64afc795fd make sure voluntary releases don't get allocated to L2WritebackUnit 2016-07-06 14:10:45 -07:00
Howard Mao b105076996 fix ID mapper to disallow two in-flight requests with the same inner ID 2016-07-05 17:41:46 -07:00
Howard Mao af76837970 conform to new NastiWriteDataChannel interface 2016-07-05 17:41:46 -07:00
Howard Mao 702444709a make sure pending bits updated for all releases 2016-07-05 12:08:22 -07:00
Howard Mao 06ed9c5794 add a single-entry queue in front of acquire and release for bufferless broadcast hub 2016-07-05 12:08:22 -07:00
Howard Mao 67bac383e3 hopefully fixed last bugs in Bufferless 2016-07-05 12:08:22 -07:00
Howard Mao a35388bc27 fix merging of same xact ID puts/gets 2016-07-05 12:08:22 -07:00
Howard Mao 51f7bf1511 fix Bufferless voluntary release issue 2016-07-05 12:08:22 -07:00
Howard Mao afc51c4a35 make sure TL -> NASTI converter handles multibeat transactions properly 2016-07-05 12:08:22 -07:00
Howard Mao caa9ca24b9 NASTI -> TL converter also uses ID mapper 2016-07-01 18:11:29 -07:00
Howard Mao e163a23583 fix another bug in Widener 2016-07-01 16:24:48 -07:00
Howard Mao 10a46a36ae fix full_addr() function in TileLink 2016-07-01 15:17:41 -07:00
Howard Mao 61e3e5b45a more WIP on fixing Bufferless 2016-06-30 18:29:51 -07:00
Howard Mao 0eedffa82f WIP: Fix BufferlessBroadcastHub 2016-06-30 18:29:51 -07:00
Howard Mao ce46f523c9 make sure Widener uses proper parameters to generate acquire/grant 2016-06-30 18:17:16 -07:00
Howard Mao a0b1772404 change TileLinkWidthAdapter interface 2016-06-30 15:50:23 -07:00
Howard Mao 9feca99d5d make PutBlock wmask argument match Put 2016-06-28 13:10:46 -07:00
Howard Mao b936aa9826 refactor uncore files into separate packages 2016-06-28 13:10:46 -07:00
Howard Mao ec5b9dfc86 make sure trackers can handle case where there are no caching clients 2016-06-27 16:29:51 -07:00
Howard Mao a93a70c8ec make sure merged voluntary releases are handled properly 2016-06-27 11:40:32 -07:00
Howard Mao e3391b36b2 get rid of MuxBundle now that MuxCase and MuxLookup are fixed 2016-06-21 10:43:44 -07:00
Howard Mao 719fffff40 make sure updates from irel and iacq gated by tracker allocation 2016-06-17 17:15:02 -07:00
Howard Mao b75b6fdcda make sure no-data voluntary releases get tracked 2016-06-17 17:15:02 -07:00
Howard Mao ebe95fa827 fix wmask buffer clearing in L2 agents 2016-06-16 15:34:31 -07:00
Howard Mao aba13cee7f fix BRAM slave so that it can correctly take all TileLink requests 2016-06-16 15:34:31 -07:00
Howard Mao e716661637 make sure merged no-alloc put still allocs if original put allocs 2016-06-16 15:34:31 -07:00
Howard Mao 7e43b1d889 fix mistaken dequeueing from roq in TileLink unwrapper 2016-06-16 15:34:31 -07:00
Howard Mao 2789e60b6b fix ignt_q logic 2016-06-16 15:18:58 -07:00
Howard Mao f421e2ab11 fix TileLinkWidthAdapter 2016-06-08 09:58:23 -07:00
Howard Mao 2d66ac93d3 make sure HastiRAM cuts off the correct number of bits for word address 2016-06-06 09:26:51 -07:00
Howard Mao e8408f0a8a fix HastiRAM 2016-06-01 10:33:59 -07:00
Howard Mao 4f84d8f757 make sure to hook up finish in ClientTileLinkEnqueuer 2016-05-18 13:13:34 -07:00
Howard Mao f138819992 fix order of assignments in ManagerTileLinkNetworkPort 2016-05-11 16:45:00 -07:00
Howard Mao 14a6e470c9 transform ids in TL -> NASTI converter if necessary 2016-05-07 21:19:27 -07:00
Howard Mao 1ed6d6646d move NastiROM and HastiRAM into rom.scala and bram.scala 2016-05-06 11:31:22 -07:00
Howard Mao 77e859760c add a Hasti RAM alongside the Nasti ROM 2016-05-06 11:31:22 -07:00
Howard Mao f26c422544 assert that TileLink router has valid route 2016-05-03 12:18:06 -07:00
Howard Mao f9de99ed40 changes to match junctions no-mmio-base 2016-04-21 15:35:37 -07:00
Howard Mao 9b3faff5a5 add id field to write data channel in TL -> AXI converter 2016-04-19 09:46:31 -07:00
Howard Mao 152645b1bc use manager_id instead of client_id in GrantFromSrc and FinishToDst 2016-04-07 11:20:16 -07:00
Howard Mao f88b6932ce don't add pending reads if data is already available 2016-04-06 15:43:21 -07:00
Howard Mao 31e145eaf0 fix BroadcastHub allocation and routing 2016-04-05 16:21:18 -07:00
Howard Mao f68a7dabdf fix AXI -> TL converter 2016-04-04 19:42:25 -07:00
Howard Mao f956d4edfb NASTI does not right-justify data; fix in converter 2016-04-01 20:55:00 -07:00
Howard Mao 3083bbca21 fix TileLink arbiters and add memory interconnect and memory selector 2016-03-31 18:15:51 -07:00
Howard MaoandHenry Cook cf363b1fe4 add TileLink interconnect generator 2016-03-31 14:12:55 -07:00
Howard Mao d78066db5c chisel3 fix for split metadata 2016-03-30 22:11:19 -07:00
Howard Mao 3d990bdbef workaround for Chisel3 name-aliasing issue 2016-03-30 19:15:22 -07:00
Howard Mao 8e7f18084b switch RTC to use TileLink instead of AXI 2016-03-28 12:23:16 -07:00
Howard Mao 7f8f138d6a fix addPendingBitWhenPartialWritemask 2016-03-24 20:01:50 -07:00
Howard Mao 11bd15432a fix bug in RTC 2016-03-24 20:01:50 -07:00
Howard Mao 00b3908d92 git rid of reorder queue in narrower 2016-03-24 20:01:50 -07:00
Howard Mao 6d984273b7 finally fix all release assertions ... hopefully 2016-02-29 15:22:24 -08:00
Howard Mao 8873222e42 fix cache release assertion 2016-02-23 16:03:51 -08:00
Howard Mao f97bd70df5 add NastiIO to HostIO converter 2016-02-19 11:21:23 -08:00
Howard Mao 53ad8387cc add NASTI to TL converter 2016-02-10 11:06:52 -08:00
Howard Mao 2825b2d645 make sure TL to NASTI converter handles MT_WU 2016-02-10 11:06:41 -08:00
Howard Mao 66e9cc8c82 make sure CSR width is parameterizable 2016-02-02 12:49:58 -08:00
Howard Mao adaec18bec add TL manager for MMIO requests 2016-02-02 12:49:58 -08:00
Howard Mao c1fe188c81 some fixes to RTC 2016-02-02 12:49:58 -08:00
Howard Mao ba94010928 DMA requests should go through MMIO 2016-02-02 12:49:58 -08:00
Howard Mao 0dc8cd5b11 move ReorderQueue and DecoupledHelper to junctions 2016-01-21 15:36:22 -08:00
Howard Mao 4ff1aea288 fix more Chisel3 deprecations 2016-01-14 14:55:45 -08:00
Howard Mao c81745eb8e lowercase SMI to Smi 2016-01-11 16:18:44 -08:00
Howard Mao d0a14c6de9 separate TileLink converter/wrapper/unwrapper/narrower into separate file 2016-01-11 16:14:56 -08:00
Howard Mao 46069ea13b implement streaming DMA functionality 2016-01-06 21:37:56 -08:00
Howard Mao 872b162e1b implement DMA engine 2015-12-16 21:27:31 -08:00
Howard Mao 8a61177224 generalize TwoWayCounter 2015-12-16 21:07:30 -08:00
Howard Mao a48237f36d get rid of the rest of the PutBlock special casing in L2 2015-12-16 20:56:29 -08:00
Howard Mao ddc79674f9 fix some issues with cache request merging 2015-12-15 21:31:02 -08:00
Howard Mao e71293e2ae fix bug in narrower logic 2015-12-06 02:58:12 -08:00
Howard Mao ee6514e4f4 make sure WritebackUnit sends correct probe addresses 2015-11-21 15:55:11 -08:00
Howard Mao 04383a31f5 Revert "make sure L2MetadataArray assigns unoccupied way if available" 
This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
 2015-11-21 10:35:40 -08:00
Howard Mao 3c95afebc6 Shift set index for multi-bank configurations 
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
 2015-11-20 23:24:57 -08:00
Howard Mao 55a85cc67a make sure wmask is passed for PutBlock in broadcast hub 2015-11-20 14:09:24 -08:00
Howard Mao 941b64cd62 make partial write-masking PutBlock constructor always set alloc bit 2015-11-20 13:34:07 -08:00
Howard Mao 24f7b9f472 make sure L2MetadataArray assigns unoccupied way if available 2015-11-19 10:45:54 -08:00
Howard Mao e50c7ad306 add NASTI error assertions back in 2015-11-18 17:05:54 -08:00
Howard Mao e12efab423 skip meta_write state if no meta write pending 2015-11-13 13:50:35 -08:00
Howard Mao 7e7d688a01 make sure L2 passes no-alloc acquires through to outer memory 2015-11-12 15:40:58 -08:00
Howard Mao b3865c370a make sure correct addr_beat is sent for Get response by narrower/converter 2015-11-12 15:40:38 -08:00