make sure WritebackUnit sends correct probe addresses
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04383a31f5
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ee6514e4f4
@ -17,15 +17,16 @@ case object NSecondaryMisses extends Field[Int]
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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case object ECCCode extends Field[Option[Code]]
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case object SetIdxOffset extends Field[Int]
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case object CacheIdBits extends Field[Int]
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case object CacheId extends Field[Int]
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trait HasCacheParameters {
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implicit val p: Parameters
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val nSets = p(NSets)
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val blockOffBits = p(CacheBlockOffsetBits)
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val idxOffset = p(SetIdxOffset)
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val cacheIdBits = p(CacheIdBits)
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val idxBits = log2Up(nSets)
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val untagBits = blockOffBits + idxOffset + idxBits
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val untagBits = blockOffBits + cacheIdBits + idxBits
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val tagBits = p(PAddrBits) - untagBits
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val nWays = p(NWays)
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val wayBits = log2Up(nWays)
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@ -101,7 +102,8 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
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case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
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trait HasL2HellaCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters {
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val idxLSB = idxOffset
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val cacheId = p(CacheId)
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val idxLSB = cacheIdBits
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val idxMSB = idxLSB + idxBits - 1
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val tagLSB = idxLSB + idxBits
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//val blockAddrBits = p(TLBlockAddrBits)
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@ -979,7 +981,7 @@ class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTrac
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val xact = Reg(new L2WritebackReq)
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val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
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val xact_addr_block = Cat(xact.tag, xact.idx)
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val xact_addr_block = Cat(xact.tag, xact.idx, UInt(cacheId, cacheIdBits))
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val pending_irels =
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connectTwoWayBeatCounter(max = io.inner.tlNCachingClients, up = io.inner.probe, down = io.inner.release)._1
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