riscv/rocket-chip
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fix Bufferless voluntary release issue

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This commit is contained in:
Howard Mao 2016-07-04 16:58:49 -07:00
parent afc51c4a35
commit 51f7bf1511
2 changed files with 11 additions and 6 deletions
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6
uncore/src/main/scala/agents/Bufferless.scala
View File

@ -74,9 +74,9 @@ class BufferlessBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Par
// A release beat can be accepted if we are idle, if its a mergeable transaction, or if its a tail beat
// and if the outer relase path is clear
val irel_could_accept = state === s_idle || irel_can_merge || irel_same_xact
io.inner.release.ready := irel_could_accept &&
(!io.irel().hasData() || io.outer.release.ready)
io.inner.release.ready := Mux(io.irel().hasData(),
(state =/= s_idle) && (irel_can_merge || irel_same_xact) && io.outer.release.ready,
(state === s_idle) || irel_can_merge || irel_same_xact)
// Dispatch outer release
outerRelease(coh = outer_coh.onHit(M_XWR), buffering = Bool(false))

11
uncore/src/main/scala/agents/Trackers.scala
View File

@ -244,11 +244,16 @@ trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
when(irel_is_allocating) {
xact_addr_block := io.irel().addr_block
// Set all of them to pending in the beginning as a precaution
// If it turns out we don't need some or all of the beats, they will
// be overridden below
pending_irel_data := ~UInt(0, innerDataBeats)
state := next
}
when(io.inner.release.fire()) {
when(io.alloc.irel.should || (irel_can_merge && io.irel().first())) {
val irel_fire = (irel_is_allocating || irel_is_merging) && io.inner.release.ready
when (irel_fire) {
when (io.irel().first()) {
xact_vol_ir_r_type := io.irel().r_type
xact_vol_ir_src := io.irel().client_id
xact_vol_ir_client_xact_id := io.irel().client_xact_id
@ -307,7 +312,7 @@ trait EmitsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
pending_orel_data(vol_ognt_counter.up.idx),
pending_orel_send),
// only writebacks need to be forwarded to the outer interface
(io.alloc.irel.should || io.alloc.irel.matches) &&
state =/= s_idle && io.alloc.irel.matches &&
io.irel().hasData() && io.inner.release.valid)
io.outer.release.bits := coh.makeVoluntaryWriteback(