riscv/rocket-chip
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fix another bug in Widener

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This commit is contained in:
Howard Mao 2016-07-01 16:24:48 -07:00
parent 10a46a36ae
commit e163a23583
1 changed files with 2 additions and 1 deletions
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3
uncore/src/main/scala/converters/Tilelink.scala
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@ -205,6 +205,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
}
val iacq = io.in.acquire.bits
val oacq = io.out.acquire.bits
val ognt = io.out.grant.bits
val ignt = io.in.grant.bits
@ -221,7 +222,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
val put_data = Reg(Vec(factor, UInt(width = innerDataBits)))
val put_wmask = Reg(Vec(factor, UInt(width = innerWriteMaskBits)))
val put_allocate = Reg(Bool())
val (put_beat, put_done) = Counter(io.out.acquire.fire() && iacq.hasMultibeatData(), outerDataBeats)
val (put_beat, put_done) = Counter(io.out.acquire.fire() && oacq.hasMultibeatData(), outerDataBeats)
val (recv_idx, recv_done) = Counter(io.in.acquire.fire() && iacq.hasMultibeatData(), factor)
val in_addr = iacq.full_addr()