move ReorderQueue and DecoupledHelper to junctions
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2946bc928e
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0dc8cd5b11
@ -116,58 +116,4 @@ object FlowThroughSerializer {
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in.ready := fs.io.in.ready
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fs.io.out
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}
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}
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class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
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val data = dType.cloneType
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val tag = UInt(width = tagWidth)
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override def cloneType =
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new ReorderQueueWrite(dType, tagWidth).asInstanceOf[this.type]
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}
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class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
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extends Module {
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val io = new Bundle {
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val enq = Decoupled(new ReorderQueueWrite(dType, tagWidth)).flip
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val deq = new Bundle {
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val valid = Bool(INPUT)
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val tag = UInt(INPUT, tagWidth)
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val data = dType.cloneType.asOutput
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val matches = Bool(OUTPUT)
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}
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}
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val roq_data = Reg(Vec(size, dType.cloneType))
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val roq_tags = Reg(Vec(size, UInt(width = tagWidth)))
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val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
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val roq_enq_addr = PriorityEncoder(roq_free)
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val roq_matches = roq_tags.zip(roq_free)
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.map { case (tag, free) => tag === io.deq.tag && !free }
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val roq_deq_addr = PriorityEncoder(roq_matches)
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io.enq.ready := roq_free.reduce(_ || _)
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io.deq.data := roq_data(roq_deq_addr)
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io.deq.matches := roq_matches.reduce(_ || _)
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when (io.enq.valid && io.enq.ready) {
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roq_data(roq_enq_addr) := io.enq.bits.data
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roq_tags(roq_enq_addr) := io.enq.bits.tag
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roq_free(roq_enq_addr) := Bool(false)
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}
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when (io.deq.valid) {
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roq_free(roq_deq_addr) := Bool(true)
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}
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}
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object DecoupledHelper {
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def apply(rvs: Bool*) = new DecoupledHelper(rvs)
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}
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class DecoupledHelper(val rvs: Seq[Bool]) {
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def fire(exclude: Bool, includes: Bool*) = {
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(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
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}
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}
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