add option to log L2 cache transactions for easier debugging
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@ -6,9 +6,11 @@ import Chisel._
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import uncore.coherence._
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import uncore.tilelink._
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import uncore.util._
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import cde.Parameters
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import cde.{Field, Parameters}
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import scala.math.max
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case object EnableL2Logging extends Field[Boolean]
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class TrackerAllocation extends Bundle {
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val matches = Bool(OUTPUT)
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val can = Bool(OUTPUT)
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@ -265,6 +267,12 @@ trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
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} .otherwise {
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pending_irel_data := (pending_irel_data & dropPendingBitWhenBeatHasData(io.inner.release))
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}
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if (p(EnableL2Logging)) {
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when (io.irel().hasData()) {
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printf("[release] addr_block=%x addr_beat=%d data=%x\n",
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io.irel().addr_block, io.irel().addr_beat, io.irel().data)
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}
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}
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}
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io.inner.grant.valid := Vec(s_wb_req, s_wb_resp, s_inner_probe, s_busy).contains(state) &&
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@ -486,6 +494,13 @@ trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer
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add_pending_bits
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}
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if (p(EnableL2Logging)) {
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when (io.inner.grant.fire() && io.ignt().hasData()) {
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printf("[get] addr_block=%x addr_beat=%d data=%x\n",
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xact_addr_block, io.ignt().addr_beat, io.ignt().data)
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}
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}
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// Have we finished receiving the complete inner acquire transaction?
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val iacq_finished = !(state === s_idle ||
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state === s_meta_read ||
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