riscv/rocket-chip
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lowercase SMI to Smi

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This commit is contained in:
Howard Mao 2016-01-11 16:18:44 -08:00
parent d0a14c6de9
commit c81745eb8e
2 changed files with 4 additions and 4 deletions
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4
uncore/src/main/scala/htif.scala
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@ -40,7 +40,7 @@ class HostIO(w: Int) extends Bundle {
class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores))
val csr = new SMIIO(scrDataBits, 12).flip
val csr = new SmiIO(scrDataBits, 12).flip
val debug_stats_csr = Bool(OUTPUT)
// wired directly to stats register
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
@ -51,7 +51,7 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
val host = new HostIO(w)
val cpu = Vec(new HtifIO, nCores).flip
val mem = new ClientUncachedTileLinkIO
val scr = new SMIIO(scrDataBits, scrAddrBits)
val scr = new SmiIO(scrDataBits, scrAddrBits)
}
io.host.debug_stats_csr := io.cpu.map(_.debug_stats_csr).reduce(_||_)

4
uncore/src/main/scala/scr.scala
View File

@ -1,7 +1,7 @@
package uncore
import Chisel._
import junctions.{SMIIO, MMIOBase}
import junctions.{SmiIO, MMIOBase}
import cde.Parameters
class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
@ -13,7 +13,7 @@ class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
class SCRFile(implicit p: Parameters) extends HtifModule()(p) {
val io = new Bundle {
val smi = new SMIIO(scrDataBits, scrAddrBits).flip
val smi = new SmiIO(scrDataBits, scrAddrBits).flip
val scr = new SCRIO
}