riscv/rocket-chip
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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
600 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
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Howard Mao f138819992 fix order of assignments in ManagerTileLinkNetworkPort
2016-05-11 16:45:00 -07:00
uncore fix order of assignments in ManagerTileLinkNetworkPort 2016-05-11 16:45:00 -07:00