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riscv
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rocket-chip
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f138819992a12893fc388d7a6eaa544e8b497789
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Howard Mao
f138819992
fix order of assignments in ManagerTileLinkNetworkPort
2016-05-11 16:45:00 -07:00
uncore
fix order of assignments in ManagerTileLinkNetworkPort
2016-05-11 16:45:00 -07:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%