get rid of MuxBundle now that MuxCase and MuxLookup are fixed
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719fffff40
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@ -197,7 +197,7 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
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def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = {
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val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
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MuxBundle(meta, Array(
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MuxCase(meta, Array(
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incoming.is(releaseInvalidateData) -> popped,
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incoming.is(releaseInvalidateAck) -> popped))
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}
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@ -299,7 +299,7 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
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def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = {
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val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
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MuxBundle(meta, Array(
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MuxCase(meta, Array(
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incoming.is(releaseInvalidateData) -> popped,
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incoming.is(releaseInvalidateAck) -> popped))
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}
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@ -417,7 +417,7 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
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def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = {
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val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
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MuxBundle(meta, Array(
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MuxCase(meta, Array(
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incoming.is(releaseInvalidateData) -> popped,
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incoming.is(releaseInvalidateAck) -> popped))
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}
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@ -537,7 +537,7 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
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def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = {
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val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
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MuxBundle(meta, Array(
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MuxCase(meta, Array(
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incoming.is(releaseInvalidateData) -> popped,
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incoming.is(releaseInvalidateAck) -> popped))
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}
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@ -680,7 +680,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
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def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = {
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val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
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MuxBundle(meta, Array(
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MuxCase(meta, Array(
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incoming.is(releaseInvalidateData) -> popped,
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incoming.is(releaseInvalidateAck) -> popped,
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incoming.is(releaseInvalidateDataMigratory) -> popped,
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@ -887,7 +887,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
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wmask = put_wmask.toBits)
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io.out.acquire.valid := sending_put || (!shrink && io.in.acquire.valid)
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io.out.acquire.bits := MuxBundle(get_block_acquire, Seq(
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io.out.acquire.bits := MuxCase(get_block_acquire, Seq(
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sending_put -> put_block_acquire,
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smallget -> get_acquire,
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smallput -> put_acquire))
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@ -961,7 +961,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
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data = ognt.data)
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io.in.grant.valid := returning_data || (!stretch && io.out.grant.valid)
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io.in.grant.bits := MuxBundle(default_grant, Seq(
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io.in.grant.bits := MuxCase(default_grant, Seq(
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returning_data -> get_block_grant,
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smallgnt -> get_grant))
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io.out.grant.ready := !returning_data && (stretch || io.in.grant.ready)
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@ -1085,7 +1085,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
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val pass_valid = io.in.acquire.valid && !stretch
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io.out.acquire.bits := MuxBundle(Wire(io.out.acquire.bits, init=iacq), Seq(
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io.out.acquire.bits := MuxCase(Wire(io.out.acquire.bits, init=iacq), Seq(
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(sending_put, put_block_acquire),
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(shrink, get_block_acquire),
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(smallput, put_acquire),
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@ -1138,7 +1138,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
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io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
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io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)
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io.in.grant.bits := MuxBundle(Wire(io.in.grant.bits, init=ognt), Seq(
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io.in.grant.bits := MuxCase(Wire(io.in.grant.bits, init=ognt), Seq(
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sending_get -> get_block_grant,
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smallget_grant -> get_grant))
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@ -369,7 +369,7 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
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io.mem.acquire.valid := (state === s_get) ||
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(state === s_put && get_done) ||
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(state === s_prefetch && !prefetch_busy(prefetch_id))
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io.mem.acquire.bits := MuxBundle(
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io.mem.acquire.bits := MuxLookup(
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state, prefetch_acquire, Seq(
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s_get -> get_acquire,
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s_put -> put_acquire))
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@ -4,16 +4,6 @@ package uncore
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import Chisel._
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object MuxBundle {
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def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
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mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b))
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}
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def apply[T <: Data] (key: UInt, default: T, mapping: Seq[(UInt, T)]): T = {
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apply(default, mapping.map{ case (a, b) => (a === key, b) })
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}
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}
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// Produces 0-width value when counting to 1
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class ZCounter(val n: Int) {
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val value = Reg(init=UInt(0, log2Ceil(n)))
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