separate TileLink converter/wrapper/unwrapper/narrower into separate file
This commit is contained in:
Howard Mao
parent
46069ea13b
commit
d0a14c6de9
730
uncore/src/main/scala/converters.scala
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730
uncore/src/main/scala/converters.scala
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@ -0,0 +1,730 @@
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package uncore
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import Chisel._
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import junctions._
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import cde.Parameters
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/** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */
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object TileLinkIOWrapper {
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def apply(tl: ClientUncachedTileLinkIO)(implicit p: Parameters): ClientTileLinkIO = {
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val conv = Module(new ClientTileLinkIOWrapper)
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conv.io.in <> tl
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conv.io.out
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}
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def apply(tl: UncachedTileLinkIO)(implicit p: Parameters): TileLinkIO = {
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val conv = Module(new TileLinkIOWrapper)
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conv.io.in <> tl
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conv.io.out
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}
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def apply(tl: ClientTileLinkIO): ClientTileLinkIO = tl
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def apply(tl: TileLinkIO): TileLinkIO = tl
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}
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class TileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val in = new UncachedTileLinkIO().flip
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val out = new TileLinkIO
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}
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io.out.acquire <> io.in.acquire
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io.in.grant <> io.out.grant
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io.out.finish <> io.in.finish
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io.out.probe.ready := Bool(true)
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io.out.release.valid := Bool(false)
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}
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class ClientTileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val in = new ClientUncachedTileLinkIO().flip
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val out = new ClientTileLinkIO
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}
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io.out.acquire <> io.in.acquire
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io.in.grant <> io.out.grant
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io.out.probe.ready := Bool(true)
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io.out.release.valid := Bool(false)
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}
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/** A helper module that automatically issues [[uncore.Finish]] messages in repsonse
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* to [[uncore.Grant]] that it receives from a manager and forwards to a client
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*/
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class FinishUnit(srcId: Int = 0, outstanding: Int = 2)(implicit p: Parameters) extends TLModule()(p)
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with HasDataBeatCounters {
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val io = new Bundle {
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val grant = Decoupled(new LogicalNetworkIO(new Grant)).flip
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val refill = Decoupled(new Grant)
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val finish = Decoupled(new LogicalNetworkIO(new Finish))
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val ready = Bool(OUTPUT)
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}
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val g = io.grant.bits.payload
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if(tlNetworkPreservesPointToPointOrdering) {
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io.finish.valid := Bool(false)
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io.refill.valid := io.grant.valid
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io.refill.bits := g
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io.grant.ready := io.refill.ready
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io.ready := Bool(true)
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} else {
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// We only want to send Finishes after we have collected all beats of
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// a multibeat Grant. But Grants from multiple managers or transactions may
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// get interleaved, so we could need a counter for each.
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val done = if(tlNetworkDoesNotInterleaveBeats) {
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connectIncomingDataBeatCounterWithHeader(io.grant)
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} else {
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val entries = 1 << tlClientXactIdBits
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def getId(g: LogicalNetworkIO[Grant]) = g.payload.client_xact_id
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assert(getId(io.grant.bits) <= UInt(entries), "Not enough grant beat counters, only " + entries + " entries.")
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connectIncomingDataBeatCountersWithHeader(io.grant, entries, getId).reduce(_||_)
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}
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val q = Module(new FinishQueue(outstanding))
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q.io.enq.valid := io.grant.fire() && g.requiresAck() && (!g.hasMultibeatData() || done)
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q.io.enq.bits.fin := g.makeFinish()
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q.io.enq.bits.dst := io.grant.bits.header.src
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io.finish.bits.header.src := UInt(srcId)
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io.finish.bits.header.dst := q.io.deq.bits.dst
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io.finish.bits.payload := q.io.deq.bits.fin
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io.finish.valid := q.io.deq.valid
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q.io.deq.ready := io.finish.ready
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io.refill.valid := (q.io.enq.ready || !g.requiresAck()) && io.grant.valid
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io.refill.bits := g
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io.grant.ready := (q.io.enq.ready || !g.requiresAck()) && io.refill.ready
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io.ready := q.io.enq.ready
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}
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}
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class FinishQueueEntry(implicit p: Parameters) extends TLBundle()(p) {
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val fin = new Finish
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val dst = UInt(width = log2Up(p(LNEndpoints)))
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}
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class FinishQueue(entries: Int)(implicit p: Parameters) extends Queue(new FinishQueueEntry()(p), entries)
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/** A port to convert [[uncore.ClientTileLinkIO]].flip into [[uncore.TileLinkIO]]
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*
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* Creates network headers for [[uncore.Acquire]] and [[uncore.Release]] messages,
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* calculating header.dst and filling in header.src.
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* Strips headers from [[uncore.Probe Probes]].
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* Responds to [[uncore.Grant]] by automatically issuing [[uncore.Finish]] to the granting managers.
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*
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* @param clientId network port id of this agent
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* @param addrConvert how a physical address maps to a destination manager port id
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*/
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class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt)
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(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val client = new ClientTileLinkIO().flip
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val network = new TileLinkIO
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}
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val finisher = Module(new FinishUnit(clientId))
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finisher.io.grant <> io.network.grant
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io.network.finish <> finisher.io.finish
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val acq_with_header = ClientTileLinkHeaderCreator(io.client.acquire, clientId, addrConvert)
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val rel_with_header = ClientTileLinkHeaderCreator(io.client.release, clientId, addrConvert)
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val prb_without_header = DecoupledLogicalNetworkIOUnwrapper(io.network.probe)
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val gnt_without_header = finisher.io.refill
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io.network.acquire.bits := acq_with_header.bits
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io.network.acquire.valid := acq_with_header.valid && finisher.io.ready
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acq_with_header.ready := io.network.acquire.ready && finisher.io.ready
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io.network.release <> rel_with_header
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io.client.probe <> prb_without_header
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io.client.grant <> gnt_without_header
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}
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object ClientTileLinkHeaderCreator {
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def apply[T <: ClientToManagerChannel with HasCacheBlockAddress](
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in: DecoupledIO[T],
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clientId: Int,
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addrConvert: UInt => UInt)
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(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
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out.bits.payload := in.bits
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out.bits.header.src := UInt(clientId)
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out.bits.header.dst := addrConvert(in.bits.addr_block)
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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}
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/** A port to convert [[uncore.ManagerTileLinkIO]].flip into [[uncore.TileLinkIO]].flip
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*
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* Creates network headers for [[uncore.Probe]] and [[uncore.Grant]] messagess,
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* calculating header.dst and filling in header.src.
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* Strips headers from [[uncore.Acquire]], [[uncore.Release]] and [[uncore.Finish]],
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* but supplies client_id instead.
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*
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* @param managerId the network port id of this agent
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* @param idConvert how a sharer id maps to a destination client port id
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*/
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class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt)
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(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val manager = new ManagerTileLinkIO().flip
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val network = new TileLinkIO().flip
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}
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io.network.grant <> ManagerTileLinkHeaderCreator(io.manager.grant, managerId, (u: UInt) => u)
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io.network.probe <> ManagerTileLinkHeaderCreator(io.manager.probe, managerId, idConvert)
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io.manager.acquire.bits.client_id := io.network.acquire.bits.header.src
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io.manager.acquire <> DecoupledLogicalNetworkIOUnwrapper(io.network.acquire)
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io.manager.release.bits.client_id := io.network.release.bits.header.src
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io.manager.release <> DecoupledLogicalNetworkIOUnwrapper(io.network.release)
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io.manager.finish <> DecoupledLogicalNetworkIOUnwrapper(io.network.finish)
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}
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object ManagerTileLinkHeaderCreator {
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def apply[T <: ManagerToClientChannel with HasClientId](
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in: DecoupledIO[T],
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managerId: Int,
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idConvert: UInt => UInt)
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(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
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out.bits.payload := in.bits
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out.bits.header.src := UInt(managerId)
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out.bits.header.dst := idConvert(in.bits.client_id)
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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}
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/** Utility trait containing wiring functions to keep track of how many data beats have
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* been sent or recieved over a particular [[uncore.TileLinkChannel]] or pair of channels.
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*
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* Won't count message types that don't have data.
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* Used in [[uncore.XactTracker]] and [[uncore.FinishUnit]].
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*/
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trait HasDataBeatCounters {
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type HasBeat = TileLinkChannel with HasTileLinkBeatId
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/** Returns the current count on this channel and when a message is done
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* @param inc increment the counter (usually .valid or .fire())
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* @param data the actual channel data
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* @param beat count to return for single-beat messages
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*/
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def connectDataBeatCounter[S <: TileLinkChannel](inc: Bool, data: S, beat: UInt) = {
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val multi = data.hasMultibeatData()
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val (multi_cnt, multi_done) = Counter(inc && multi, data.tlDataBeats)
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val cnt = Mux(multi, multi_cnt, beat)
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val done = Mux(multi, multi_done, inc)
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(cnt, done)
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}
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/** Counter for beats on outgoing [[chisel.DecoupledIO]] */
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def connectOutgoingDataBeatCounter[T <: TileLinkChannel](
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out: DecoupledIO[T],
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beat: UInt = UInt(0)): (UInt, Bool) =
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connectDataBeatCounter(out.fire(), out.bits, beat)
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/** Returns done but not cnt. Use the addr_beat subbundle instead of cnt for beats on
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* incoming channels in case of network reordering.
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*/
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def connectIncomingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T]): Bool =
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connectDataBeatCounter(in.fire(), in.bits, UInt(0))._2
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/** Counter for beats on incoming DecoupledIO[LogicalNetworkIO[]]s returns done */
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def connectIncomingDataBeatCounterWithHeader[T <: TileLinkChannel](in: DecoupledIO[LogicalNetworkIO[T]]): Bool =
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connectDataBeatCounter(in.fire(), in.bits.payload, UInt(0))._2
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/** If the network might interleave beats from different messages, we need a Vec of counters,
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* one for every outstanding message id that might be interleaved.
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*
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* @param getId mapping from Message to counter id
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*/
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def connectIncomingDataBeatCountersWithHeader[T <: TileLinkChannel with HasClientTransactionId](
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in: DecoupledIO[LogicalNetworkIO[T]],
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entries: Int,
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getId: LogicalNetworkIO[T] => UInt): Vec[Bool] = {
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Vec((0 until entries).map { i =>
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connectDataBeatCounter(in.fire() && getId(in.bits) === UInt(i), in.bits.payload, UInt(0))._2
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})
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}
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/** Provides counters on two channels, as well a meta-counter that tracks how many
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* messages have been sent over the up channel but not yet responded to over the down channel
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*
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* @param max max number of outstanding ups with no down
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* @param up outgoing channel
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* @param down incoming channel
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* @param beat overrides cnts on single-beat messages
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* @param track whether up's message should be tracked
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* @return a tuple containing whether their are outstanding messages, up's count,
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* up's done, down's count, down's done
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*/
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def connectTwoWayBeatCounter[T <: TileLinkChannel, S <: TileLinkChannel](
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max: Int,
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up: DecoupledIO[T],
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down: DecoupledIO[S],
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beat: UInt = UInt(0),
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track: T => Bool = (t: T) => Bool(true)): (Bool, UInt, Bool, UInt, Bool) = {
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val (up_idx, up_done) = connectDataBeatCounter(up.fire(), up.bits, beat)
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val (down_idx, down_done) = connectDataBeatCounter(down.fire(), down.bits, beat)
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val do_inc = up_done && track(up.bits)
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val do_dec = down_done
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val cnt = TwoWayCounter(do_inc, do_dec, max)
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(cnt > UInt(0), up_idx, up_done, down_idx, down_done)
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}
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}
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class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val in = new ClientTileLinkIO().flip
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val out = new ClientUncachedTileLinkIO
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}
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def needsRoqEnq(channel: HasTileLinkData): Bool =
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!channel.hasMultibeatData() || channel.addr_beat === UInt(0)
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def needsRoqDeq(channel: HasTileLinkData): Bool =
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!channel.hasMultibeatData() || channel.addr_beat === UInt(tlDataBeats - 1)
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val acqArb = Module(new LockingRRArbiter(new Acquire, 2, tlDataBeats,
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Some((acq: Acquire) => acq.hasMultibeatData())))
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val acqRoq = Module(new ReorderQueue(
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Bool(), tlClientXactIdBits, tlMaxClientsPerPort))
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val relRoq = Module(new ReorderQueue(
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Bool(), tlClientXactIdBits, tlMaxClientsPerPort))
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val iacq = io.in.acquire.bits
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val irel = io.in.release.bits
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val ognt = io.out.grant.bits
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val acq_roq_enq = needsRoqEnq(iacq)
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val rel_roq_enq = needsRoqEnq(irel)
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val acq_roq_ready = !acq_roq_enq || acqRoq.io.enq.ready
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val rel_roq_ready = !rel_roq_enq || relRoq.io.enq.ready
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val acq_helper = DecoupledHelper(
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io.in.acquire.valid,
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acq_roq_ready,
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acqArb.io.in(0).ready)
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val rel_helper = DecoupledHelper(
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io.in.release.valid,
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rel_roq_ready,
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acqArb.io.in(1).ready)
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acqRoq.io.enq.valid := acq_helper.fire(acq_roq_ready, acq_roq_enq)
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acqRoq.io.enq.bits.data := iacq.isBuiltInType()
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acqRoq.io.enq.bits.tag := iacq.client_xact_id
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acqArb.io.in(0).valid := acq_helper.fire(acqArb.io.in(0).ready)
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acqArb.io.in(0).bits := Acquire(
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is_builtin_type = Bool(true),
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a_type = Mux(iacq.isBuiltInType(),
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iacq.a_type, Acquire.getBlockType),
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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addr_beat = iacq.addr_beat,
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data = iacq.data,
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union = Mux(iacq.isBuiltInType(),
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iacq.union, Cat(MT_Q, M_XRD, Bool(true))))
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io.in.acquire.ready := acq_helper.fire(io.in.acquire.valid)
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relRoq.io.enq.valid := rel_helper.fire(rel_roq_ready, rel_roq_enq)
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relRoq.io.enq.bits.data := irel.isVoluntary()
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relRoq.io.enq.bits.tag := irel.client_xact_id
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acqArb.io.in(1).valid := rel_helper.fire(acqArb.io.in(1).ready)
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acqArb.io.in(1).bits := PutBlock(
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client_xact_id = irel.client_xact_id,
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addr_block = irel.addr_block,
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addr_beat = irel.addr_beat,
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data = irel.data,
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wmask = Acquire.fullWriteMask)
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io.in.release.ready := rel_helper.fire(io.in.release.valid)
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io.out.acquire <> acqArb.io.out
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acqRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt)
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acqRoq.io.deq.tag := ognt.client_xact_id
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relRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt)
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relRoq.io.deq.tag := ognt.client_xact_id
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val gnt_builtin = acqRoq.io.deq.data
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val gnt_voluntary = relRoq.io.deq.data
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val acq_grant = Grant(
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is_builtin_type = gnt_builtin,
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g_type = Mux(gnt_builtin, ognt.g_type, tlCoh.getExclusiveGrantType),
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client_xact_id = ognt.client_xact_id,
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manager_xact_id = ognt.manager_xact_id,
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addr_beat = ognt.addr_beat,
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data = ognt.data)
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val rel_grant = Grant(
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is_builtin_type = Bool(true),
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g_type = Mux(gnt_voluntary, Grant.voluntaryAckType, ognt.g_type),
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client_xact_id = ognt.client_xact_id,
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manager_xact_id = ognt.manager_xact_id,
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addr_beat = ognt.addr_beat,
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data = ognt.data)
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io.in.grant.valid := io.out.grant.valid
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io.in.grant.bits := Mux(acqRoq.io.deq.matches, acq_grant, rel_grant)
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io.out.grant.ready := io.in.grant.ready
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io.in.probe.valid := Bool(false)
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}
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class NastiIOTileLinkIOConverterInfo(implicit p: Parameters) extends TLBundle()(p) {
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val addr_beat = UInt(width = tlBeatAddrBits)
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val byteOff = UInt(width = tlByteAddrBits)
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val subblock = Bool()
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}
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class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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with HasNastiParameters {
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val nasti = new NastiIO
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}
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private def opSizeToXSize(ops: UInt) = MuxLookup(ops, UInt("b111"), Seq(
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MT_B -> UInt(0),
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MT_BU -> UInt(0),
|
||||
MT_H -> UInt(1),
|
||||
MT_HU -> UInt(1),
|
||||
MT_W -> UInt(2),
|
||||
MT_D -> UInt(3),
|
||||
MT_Q -> UInt(log2Up(tlDataBytes))))
|
||||
|
||||
val dataBits = tlDataBits*tlDataBeats
|
||||
require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
|
||||
require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
|
||||
require(tlClientXactIdBits <= nastiXIdBits, "NastiIO converter is going truncate tags: " + tlClientXactIdBits + " > " + nastiXIdBits)
|
||||
|
||||
val has_data = io.tl.acquire.bits.hasData()
|
||||
|
||||
val is_subblock = io.tl.acquire.bits.isSubBlockType()
|
||||
val is_multibeat = io.tl.acquire.bits.hasMultibeatData()
|
||||
val (tl_cnt_out, tl_wrap_out) = Counter(
|
||||
io.tl.acquire.fire() && is_multibeat, tlDataBeats)
|
||||
|
||||
val get_valid = io.tl.acquire.valid && !has_data
|
||||
val put_valid = io.tl.acquire.valid && has_data
|
||||
|
||||
// Reorder queue saves extra information needed to send correct
|
||||
// grant back to TL client
|
||||
val roq = Module(new ReorderQueue(
|
||||
new NastiIOTileLinkIOConverterInfo,
|
||||
nastiRIdBits, tlMaxClientsPerPort))
|
||||
|
||||
// For Get/GetBlock, make sure Reorder queue can accept new entry
|
||||
val get_helper = DecoupledHelper(
|
||||
get_valid,
|
||||
roq.io.enq.ready,
|
||||
io.nasti.ar.ready)
|
||||
|
||||
val w_inflight = Reg(init = Bool(false))
|
||||
|
||||
// For Put/PutBlock, make sure aw and w channel are both ready before
|
||||
// we send the first beat
|
||||
val aw_ready = w_inflight || io.nasti.aw.ready
|
||||
val put_helper = DecoupledHelper(
|
||||
put_valid,
|
||||
aw_ready,
|
||||
io.nasti.w.ready)
|
||||
|
||||
val (nasti_cnt_out, nasti_wrap_out) = Counter(
|
||||
io.nasti.r.fire() && !roq.io.deq.data.subblock, tlDataBeats)
|
||||
|
||||
roq.io.enq.valid := get_helper.fire(roq.io.enq.ready)
|
||||
roq.io.enq.bits.tag := io.nasti.ar.bits.id
|
||||
roq.io.enq.bits.data.addr_beat := io.tl.acquire.bits.addr_beat
|
||||
roq.io.enq.bits.data.byteOff := io.tl.acquire.bits.addr_byte()
|
||||
roq.io.enq.bits.data.subblock := is_subblock
|
||||
roq.io.deq.valid := io.nasti.r.fire() && (nasti_wrap_out || roq.io.deq.data.subblock)
|
||||
roq.io.deq.tag := io.nasti.r.bits.id
|
||||
|
||||
// Decompose outgoing TL Acquires into Nasti address and data channels
|
||||
io.nasti.ar.valid := get_helper.fire(io.nasti.ar.ready)
|
||||
io.nasti.ar.bits := NastiReadAddressChannel(
|
||||
id = io.tl.acquire.bits.client_xact_id,
|
||||
addr = io.tl.acquire.bits.full_addr(),
|
||||
size = Mux(is_subblock,
|
||||
opSizeToXSize(io.tl.acquire.bits.op_size()),
|
||||
UInt(log2Ceil(tlDataBytes))),
|
||||
len = Mux(is_subblock, UInt(0), UInt(tlDataBeats - 1)))
|
||||
|
||||
io.nasti.aw.valid := put_helper.fire(aw_ready, !w_inflight)
|
||||
io.nasti.aw.bits := NastiWriteAddressChannel(
|
||||
id = io.tl.acquire.bits.client_xact_id,
|
||||
addr = io.tl.acquire.bits.full_addr(),
|
||||
size = UInt(log2Ceil(tlDataBytes)),
|
||||
len = Mux(is_multibeat, UInt(tlDataBeats - 1), UInt(0)))
|
||||
|
||||
io.nasti.w.valid := put_helper.fire(io.nasti.w.ready)
|
||||
io.nasti.w.bits := NastiWriteDataChannel(
|
||||
data = io.tl.acquire.bits.data,
|
||||
strb = io.tl.acquire.bits.wmask(),
|
||||
last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock))
|
||||
|
||||
io.tl.acquire.ready := Mux(has_data,
|
||||
put_helper.fire(put_valid),
|
||||
get_helper.fire(get_valid))
|
||||
|
||||
when (!w_inflight && io.tl.acquire.fire() && is_multibeat) {
|
||||
w_inflight := Bool(true)
|
||||
}
|
||||
|
||||
when (w_inflight) {
|
||||
when (tl_wrap_out) { w_inflight := Bool(false) }
|
||||
}
|
||||
|
||||
// Aggregate incoming NASTI responses into TL Grants
|
||||
val (tl_cnt_in, tl_wrap_in) = Counter(
|
||||
io.tl.grant.fire() && io.tl.grant.bits.hasMultibeatData(), tlDataBeats)
|
||||
val gnt_arb = Module(new Arbiter(new GrantToDst, 2))
|
||||
io.tl.grant <> gnt_arb.io.out
|
||||
|
||||
val r_aligned_data = Mux(roq.io.deq.data.subblock,
|
||||
io.nasti.r.bits.data << Cat(roq.io.deq.data.byteOff, UInt(0, 3)),
|
||||
io.nasti.r.bits.data)
|
||||
|
||||
gnt_arb.io.in(0).valid := io.nasti.r.valid
|
||||
io.nasti.r.ready := gnt_arb.io.in(0).ready
|
||||
gnt_arb.io.in(0).bits := Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Mux(roq.io.deq.data.subblock,
|
||||
Grant.getDataBeatType, Grant.getDataBlockType),
|
||||
client_xact_id = io.nasti.r.bits.id,
|
||||
manager_xact_id = UInt(0),
|
||||
addr_beat = Mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in),
|
||||
data = r_aligned_data)
|
||||
|
||||
gnt_arb.io.in(1).valid := io.nasti.b.valid
|
||||
io.nasti.b.ready := gnt_arb.io.in(1).ready
|
||||
gnt_arb.io.in(1).bits := Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Grant.putAckType,
|
||||
client_xact_id = io.nasti.b.bits.id,
|
||||
manager_xact_id = UInt(0),
|
||||
addr_beat = UInt(0),
|
||||
data = Bits(0))
|
||||
|
||||
assert(!io.nasti.r.valid || io.nasti.r.bits.resp === UInt(0), "NASTI read error")
|
||||
assert(!io.nasti.b.valid || io.nasti.b.bits.resp === UInt(0), "NASTI write error")
|
||||
}
|
||||
|
||||
class TileLinkIONarrower(innerTLId: String, outerTLId: String)
|
||||
(implicit p: Parameters) extends TLModule()(p) {
|
||||
|
||||
val innerParams = p(TLKey(innerTLId))
|
||||
val outerParams = p(TLKey(outerTLId))
|
||||
val innerDataBeats = innerParams.dataBeats
|
||||
val innerDataBits = innerParams.dataBitsPerBeat
|
||||
val innerWriteMaskBits = innerParams.writeMaskBits
|
||||
val innerByteAddrBits = log2Up(innerWriteMaskBits)
|
||||
val outerDataBeats = outerParams.dataBeats
|
||||
val outerDataBits = outerParams.dataBitsPerBeat
|
||||
val outerWriteMaskBits = outerParams.writeMaskBits
|
||||
val outerByteAddrBits = log2Up(outerWriteMaskBits)
|
||||
val outerBeatAddrBits = log2Up(outerDataBeats)
|
||||
val outerBlockOffset = outerBeatAddrBits + outerByteAddrBits
|
||||
val outerMaxClients = outerParams.maxClientsPerPort
|
||||
val outerIdBits = log2Up(outerParams.maxClientXacts * outerMaxClients)
|
||||
|
||||
require(outerDataBeats >= innerDataBeats)
|
||||
require(outerDataBeats % innerDataBeats == 0)
|
||||
require(outerDataBits <= innerDataBits)
|
||||
require(outerDataBits * outerDataBeats == innerDataBits * innerDataBeats)
|
||||
|
||||
val factor = outerDataBeats / innerDataBeats
|
||||
|
||||
val io = new Bundle {
|
||||
val in = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => innerTLId})).flip
|
||||
val out = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => outerTLId}))
|
||||
}
|
||||
|
||||
if (factor > 1) {
|
||||
val iacq = io.in.acquire.bits
|
||||
val ognt = io.out.grant.bits
|
||||
|
||||
val stretch = iacq.a_type === Acquire.putBlockType
|
||||
val shrink = iacq.a_type === Acquire.getBlockType
|
||||
val smallput = iacq.a_type === Acquire.putType
|
||||
val smallget = iacq.a_type === Acquire.getType
|
||||
|
||||
val acq_data_buffer = Reg(UInt(width = innerDataBits))
|
||||
val acq_wmask_buffer = Reg(UInt(width = innerWriteMaskBits))
|
||||
val acq_client_id = Reg(iacq.client_xact_id)
|
||||
val acq_addr_block = Reg(iacq.addr_block)
|
||||
val acq_addr_beat = Reg(iacq.addr_beat)
|
||||
val oacq_ctr = Counter(factor)
|
||||
|
||||
// this part of the address shifts from the inner byte address
|
||||
// to the outer beat address
|
||||
val readshift = iacq.full_addr()(innerByteAddrBits - 1, outerByteAddrBits)
|
||||
val outer_beat_addr = iacq.full_addr()(outerBlockOffset - 1, outerByteAddrBits)
|
||||
val outer_byte_addr = iacq.full_addr()(outerByteAddrBits - 1, 0)
|
||||
|
||||
val mask_chunks = Vec.tabulate(factor) { i =>
|
||||
val lsb = i * outerWriteMaskBits
|
||||
val msb = (i + 1) * outerWriteMaskBits - 1
|
||||
iacq.wmask()(msb, lsb)
|
||||
}
|
||||
|
||||
val data_chunks = Vec.tabulate(factor) { i =>
|
||||
val lsb = i * outerDataBits
|
||||
val msb = (i + 1) * outerDataBits - 1
|
||||
iacq.data(msb, lsb)
|
||||
}
|
||||
|
||||
val beat_sel = Cat(mask_chunks.map(mask => mask.orR).reverse)
|
||||
|
||||
val smallput_data = Mux1H(beat_sel, data_chunks)
|
||||
val smallput_wmask = Mux1H(beat_sel, mask_chunks)
|
||||
val smallput_beat = Cat(iacq.addr_beat, PriorityEncoder(beat_sel))
|
||||
|
||||
assert(!io.in.acquire.valid || !smallput || PopCount(beat_sel) <= UInt(1),
|
||||
"Can't perform Put wider than outer width")
|
||||
|
||||
val read_size_ok = MuxLookup(iacq.op_size(), Bool(false), Seq(
|
||||
MT_B -> Bool(true),
|
||||
MT_BU -> Bool(true),
|
||||
MT_H -> Bool(outerDataBits >= 16),
|
||||
MT_HU -> Bool(outerDataBits >= 16),
|
||||
MT_W -> Bool(outerDataBits >= 32),
|
||||
MT_D -> Bool(outerDataBits >= 64),
|
||||
MT_Q -> Bool(false)))
|
||||
|
||||
assert(!io.in.acquire.valid || !smallget || read_size_ok,
|
||||
"Can't perform Get wider than outer width")
|
||||
|
||||
val outerConfig = p.alterPartial({ case TLId => outerTLId })
|
||||
val innerConfig = p.alterPartial({ case TLId => innerTLId })
|
||||
|
||||
val get_block_acquire = GetBlock(
|
||||
client_xact_id = iacq.client_xact_id,
|
||||
addr_block = iacq.addr_block,
|
||||
alloc = iacq.allocate())(outerConfig)
|
||||
|
||||
val put_block_acquire = PutBlock(
|
||||
client_xact_id = acq_client_id,
|
||||
addr_block = acq_addr_block,
|
||||
addr_beat = if (factor > 1)
|
||||
Cat(acq_addr_beat, oacq_ctr.value)
|
||||
else acq_addr_beat,
|
||||
data = acq_data_buffer(outerDataBits - 1, 0),
|
||||
wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))(outerConfig)
|
||||
|
||||
val get_acquire = Get(
|
||||
client_xact_id = iacq.client_xact_id,
|
||||
addr_block = iacq.addr_block,
|
||||
addr_beat = outer_beat_addr,
|
||||
addr_byte = outer_byte_addr,
|
||||
operand_size = iacq.op_size(),
|
||||
alloc = iacq.allocate())(outerConfig)
|
||||
|
||||
val put_acquire = Put(
|
||||
client_xact_id = iacq.client_xact_id,
|
||||
addr_block = iacq.addr_block,
|
||||
addr_beat = smallput_beat,
|
||||
data = smallput_data,
|
||||
wmask = Some(smallput_wmask))(outerConfig)
|
||||
|
||||
val sending_put = Reg(init = Bool(false))
|
||||
|
||||
val pass_valid = io.in.acquire.valid && !stretch && !smallget
|
||||
val smallget_valid = smallget && io.in.acquire.valid
|
||||
|
||||
val smallget_roq = Module(new ReorderQueue(
|
||||
readshift, outerIdBits, outerMaxClients))
|
||||
|
||||
val smallget_helper = DecoupledHelper(
|
||||
smallget_valid,
|
||||
smallget_roq.io.enq.ready,
|
||||
io.out.acquire.ready)
|
||||
|
||||
smallget_roq.io.enq.valid := smallget_helper.fire(
|
||||
smallget_roq.io.enq.ready, !sending_put)
|
||||
smallget_roq.io.enq.bits.data := readshift
|
||||
smallget_roq.io.enq.bits.tag := iacq.client_xact_id
|
||||
|
||||
io.out.acquire.bits := MuxBundle(iacq, Seq(
|
||||
(sending_put, put_block_acquire),
|
||||
(shrink, get_block_acquire),
|
||||
(smallput, put_acquire),
|
||||
(smallget, get_acquire)))
|
||||
io.out.acquire.valid := sending_put || pass_valid ||
|
||||
smallget_helper.fire(io.out.acquire.ready)
|
||||
io.in.acquire.ready := !sending_put && (stretch ||
|
||||
(!smallget && io.out.acquire.ready) ||
|
||||
smallget_helper.fire(smallget_valid))
|
||||
|
||||
when (io.in.acquire.fire() && stretch) {
|
||||
acq_data_buffer := iacq.data
|
||||
acq_wmask_buffer := iacq.wmask()
|
||||
acq_client_id := iacq.client_xact_id
|
||||
acq_addr_block := iacq.addr_block
|
||||
acq_addr_beat := iacq.addr_beat
|
||||
sending_put := Bool(true)
|
||||
}
|
||||
|
||||
when (sending_put && io.out.acquire.ready) {
|
||||
acq_data_buffer := acq_data_buffer >> outerDataBits
|
||||
acq_wmask_buffer := acq_wmask_buffer >> outerWriteMaskBits
|
||||
when (oacq_ctr.inc()) { sending_put := Bool(false) }
|
||||
}
|
||||
|
||||
val ognt_block = ognt.hasMultibeatData()
|
||||
val gnt_data_buffer = Reg(Vec(factor, UInt(width = outerDataBits)))
|
||||
val gnt_client_id = Reg(ognt.client_xact_id)
|
||||
val gnt_manager_id = Reg(ognt.manager_xact_id)
|
||||
|
||||
val ignt_ctr = Counter(innerDataBeats)
|
||||
val ognt_ctr = Counter(factor)
|
||||
val sending_get = Reg(init = Bool(false))
|
||||
|
||||
val get_block_grant = Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Grant.getDataBlockType,
|
||||
client_xact_id = gnt_client_id,
|
||||
manager_xact_id = gnt_manager_id,
|
||||
addr_beat = ignt_ctr.value,
|
||||
data = gnt_data_buffer.toBits)(innerConfig)
|
||||
|
||||
val smallget_grant = ognt.g_type === Grant.getDataBeatType
|
||||
val get_grant_shift = Cat(smallget_roq.io.deq.data,
|
||||
UInt(0, outerByteAddrBits + 3))
|
||||
|
||||
smallget_roq.io.deq.valid := io.out.grant.fire() && smallget_grant
|
||||
smallget_roq.io.deq.tag := ognt.client_xact_id
|
||||
|
||||
val get_grant = Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Grant.getDataBeatType,
|
||||
client_xact_id = ognt.client_xact_id,
|
||||
manager_xact_id = ognt.manager_xact_id,
|
||||
addr_beat = ognt.addr_beat >> UInt(log2Up(factor)),
|
||||
data = ognt.data << get_grant_shift)(innerConfig)
|
||||
|
||||
io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
|
||||
io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)
|
||||
io.in.grant.bits := MuxBundle(ognt, Seq(
|
||||
sending_get -> get_block_grant,
|
||||
smallget_grant -> get_grant))
|
||||
|
||||
when (io.out.grant.valid && ognt_block && !sending_get) {
|
||||
gnt_data_buffer(ognt_ctr.value) := ognt.data
|
||||
when (ognt_ctr.inc()) {
|
||||
gnt_client_id := ognt.client_xact_id
|
||||
gnt_manager_id := ognt.manager_xact_id
|
||||
sending_get := Bool(true)
|
||||
}
|
||||
}
|
||||
|
||||
when (io.in.grant.ready && sending_get) {
|
||||
ignt_ctr.inc()
|
||||
sending_get := Bool(false)
|
||||
}
|
||||
} else { io.out <> io.in }
|
||||
}
|
||||
@ -899,193 +899,6 @@ class ManagerTileLinkIO(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val release = new DecoupledIO(new ReleaseFromSrc).flip
|
||||
}
|
||||
|
||||
/** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */
|
||||
object TileLinkIOWrapper {
|
||||
def apply(tl: ClientUncachedTileLinkIO)(implicit p: Parameters): ClientTileLinkIO = {
|
||||
val conv = Module(new ClientTileLinkIOWrapper)
|
||||
conv.io.in <> tl
|
||||
conv.io.out
|
||||
}
|
||||
def apply(tl: UncachedTileLinkIO)(implicit p: Parameters): TileLinkIO = {
|
||||
val conv = Module(new TileLinkIOWrapper)
|
||||
conv.io.in <> tl
|
||||
conv.io.out
|
||||
}
|
||||
def apply(tl: ClientTileLinkIO): ClientTileLinkIO = tl
|
||||
def apply(tl: TileLinkIO): TileLinkIO = tl
|
||||
}
|
||||
|
||||
class TileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = new UncachedTileLinkIO().flip
|
||||
val out = new TileLinkIO
|
||||
}
|
||||
io.out.acquire <> io.in.acquire
|
||||
io.in.grant <> io.out.grant
|
||||
io.out.finish <> io.in.finish
|
||||
io.out.probe.ready := Bool(true)
|
||||
io.out.release.valid := Bool(false)
|
||||
}
|
||||
|
||||
class ClientTileLinkIOWrapper(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = new ClientUncachedTileLinkIO().flip
|
||||
val out = new ClientTileLinkIO
|
||||
}
|
||||
io.out.acquire <> io.in.acquire
|
||||
io.in.grant <> io.out.grant
|
||||
io.out.probe.ready := Bool(true)
|
||||
io.out.release.valid := Bool(false)
|
||||
}
|
||||
|
||||
/** A helper module that automatically issues [[uncore.Finish]] messages in repsonse
|
||||
* to [[uncore.Grant]] that it receives from a manager and forwards to a client
|
||||
*/
|
||||
class FinishUnit(srcId: Int = 0, outstanding: Int = 2)(implicit p: Parameters) extends TLModule()(p)
|
||||
with HasDataBeatCounters {
|
||||
val io = new Bundle {
|
||||
val grant = Decoupled(new LogicalNetworkIO(new Grant)).flip
|
||||
val refill = Decoupled(new Grant)
|
||||
val finish = Decoupled(new LogicalNetworkIO(new Finish))
|
||||
val ready = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
val g = io.grant.bits.payload
|
||||
|
||||
if(tlNetworkPreservesPointToPointOrdering) {
|
||||
io.finish.valid := Bool(false)
|
||||
io.refill.valid := io.grant.valid
|
||||
io.refill.bits := g
|
||||
io.grant.ready := io.refill.ready
|
||||
io.ready := Bool(true)
|
||||
} else {
|
||||
// We only want to send Finishes after we have collected all beats of
|
||||
// a multibeat Grant. But Grants from multiple managers or transactions may
|
||||
// get interleaved, so we could need a counter for each.
|
||||
val done = if(tlNetworkDoesNotInterleaveBeats) {
|
||||
connectIncomingDataBeatCounterWithHeader(io.grant)
|
||||
} else {
|
||||
val entries = 1 << tlClientXactIdBits
|
||||
def getId(g: LogicalNetworkIO[Grant]) = g.payload.client_xact_id
|
||||
assert(getId(io.grant.bits) <= UInt(entries), "Not enough grant beat counters, only " + entries + " entries.")
|
||||
connectIncomingDataBeatCountersWithHeader(io.grant, entries, getId).reduce(_||_)
|
||||
}
|
||||
val q = Module(new FinishQueue(outstanding))
|
||||
q.io.enq.valid := io.grant.fire() && g.requiresAck() && (!g.hasMultibeatData() || done)
|
||||
q.io.enq.bits.fin := g.makeFinish()
|
||||
q.io.enq.bits.dst := io.grant.bits.header.src
|
||||
|
||||
io.finish.bits.header.src := UInt(srcId)
|
||||
io.finish.bits.header.dst := q.io.deq.bits.dst
|
||||
io.finish.bits.payload := q.io.deq.bits.fin
|
||||
io.finish.valid := q.io.deq.valid
|
||||
q.io.deq.ready := io.finish.ready
|
||||
|
||||
io.refill.valid := (q.io.enq.ready || !g.requiresAck()) && io.grant.valid
|
||||
io.refill.bits := g
|
||||
io.grant.ready := (q.io.enq.ready || !g.requiresAck()) && io.refill.ready
|
||||
io.ready := q.io.enq.ready
|
||||
}
|
||||
}
|
||||
|
||||
class FinishQueueEntry(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val fin = new Finish
|
||||
val dst = UInt(width = log2Up(p(LNEndpoints)))
|
||||
}
|
||||
|
||||
class FinishQueue(entries: Int)(implicit p: Parameters) extends Queue(new FinishQueueEntry()(p), entries)
|
||||
|
||||
/** A port to convert [[uncore.ClientTileLinkIO]].flip into [[uncore.TileLinkIO]]
|
||||
*
|
||||
* Creates network headers for [[uncore.Acquire]] and [[uncore.Release]] messages,
|
||||
* calculating header.dst and filling in header.src.
|
||||
* Strips headers from [[uncore.Probe Probes]].
|
||||
* Responds to [[uncore.Grant]] by automatically issuing [[uncore.Finish]] to the granting managers.
|
||||
*
|
||||
* @param clientId network port id of this agent
|
||||
* @param addrConvert how a physical address maps to a destination manager port id
|
||||
*/
|
||||
class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt)
|
||||
(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val client = new ClientTileLinkIO().flip
|
||||
val network = new TileLinkIO
|
||||
}
|
||||
|
||||
val finisher = Module(new FinishUnit(clientId))
|
||||
finisher.io.grant <> io.network.grant
|
||||
io.network.finish <> finisher.io.finish
|
||||
|
||||
val acq_with_header = ClientTileLinkHeaderCreator(io.client.acquire, clientId, addrConvert)
|
||||
val rel_with_header = ClientTileLinkHeaderCreator(io.client.release, clientId, addrConvert)
|
||||
val prb_without_header = DecoupledLogicalNetworkIOUnwrapper(io.network.probe)
|
||||
val gnt_without_header = finisher.io.refill
|
||||
|
||||
io.network.acquire.bits := acq_with_header.bits
|
||||
io.network.acquire.valid := acq_with_header.valid && finisher.io.ready
|
||||
acq_with_header.ready := io.network.acquire.ready && finisher.io.ready
|
||||
io.network.release <> rel_with_header
|
||||
io.client.probe <> prb_without_header
|
||||
io.client.grant <> gnt_without_header
|
||||
}
|
||||
|
||||
object ClientTileLinkHeaderCreator {
|
||||
def apply[T <: ClientToManagerChannel with HasCacheBlockAddress](
|
||||
in: DecoupledIO[T],
|
||||
clientId: Int,
|
||||
addrConvert: UInt => UInt)
|
||||
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
|
||||
out.bits.payload := in.bits
|
||||
out.bits.header.src := UInt(clientId)
|
||||
out.bits.header.dst := addrConvert(in.bits.addr_block)
|
||||
out.valid := in.valid
|
||||
in.ready := out.ready
|
||||
out
|
||||
}
|
||||
}
|
||||
|
||||
/** A port to convert [[uncore.ManagerTileLinkIO]].flip into [[uncore.TileLinkIO]].flip
|
||||
*
|
||||
* Creates network headers for [[uncore.Probe]] and [[uncore.Grant]] messagess,
|
||||
* calculating header.dst and filling in header.src.
|
||||
* Strips headers from [[uncore.Acquire]], [[uncore.Release]] and [[uncore.Finish]],
|
||||
* but supplies client_id instead.
|
||||
*
|
||||
* @param managerId the network port id of this agent
|
||||
* @param idConvert how a sharer id maps to a destination client port id
|
||||
*/
|
||||
class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt)
|
||||
(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val manager = new ManagerTileLinkIO().flip
|
||||
val network = new TileLinkIO().flip
|
||||
}
|
||||
io.network.grant <> ManagerTileLinkHeaderCreator(io.manager.grant, managerId, (u: UInt) => u)
|
||||
io.network.probe <> ManagerTileLinkHeaderCreator(io.manager.probe, managerId, idConvert)
|
||||
io.manager.acquire.bits.client_id := io.network.acquire.bits.header.src
|
||||
io.manager.acquire <> DecoupledLogicalNetworkIOUnwrapper(io.network.acquire)
|
||||
io.manager.release.bits.client_id := io.network.release.bits.header.src
|
||||
io.manager.release <> DecoupledLogicalNetworkIOUnwrapper(io.network.release)
|
||||
io.manager.finish <> DecoupledLogicalNetworkIOUnwrapper(io.network.finish)
|
||||
}
|
||||
|
||||
object ManagerTileLinkHeaderCreator {
|
||||
def apply[T <: ManagerToClientChannel with HasClientId](
|
||||
in: DecoupledIO[T],
|
||||
managerId: Int,
|
||||
idConvert: UInt => UInt)
|
||||
(implicit p: Parameters): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
val out = Wire(new DecoupledIO(new LogicalNetworkIO(in.bits)))
|
||||
out.bits.payload := in.bits
|
||||
out.bits.header.src := UInt(managerId)
|
||||
out.bits.header.dst := idConvert(in.bits.client_id)
|
||||
out.valid := in.valid
|
||||
in.ready := out.ready
|
||||
out
|
||||
}
|
||||
}
|
||||
|
||||
/** Struct for describing per-channel queue depths */
|
||||
case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)
|
||||
|
||||
@ -1316,541 +1129,3 @@ class ClientTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends
|
||||
hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
|
||||
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
||||
}
|
||||
|
||||
/** Utility trait containing wiring functions to keep track of how many data beats have
|
||||
* been sent or recieved over a particular [[uncore.TileLinkChannel]] or pair of channels.
|
||||
*
|
||||
* Won't count message types that don't have data.
|
||||
* Used in [[uncore.XactTracker]] and [[uncore.FinishUnit]].
|
||||
*/
|
||||
trait HasDataBeatCounters {
|
||||
type HasBeat = TileLinkChannel with HasTileLinkBeatId
|
||||
|
||||
/** Returns the current count on this channel and when a message is done
|
||||
* @param inc increment the counter (usually .valid or .fire())
|
||||
* @param data the actual channel data
|
||||
* @param beat count to return for single-beat messages
|
||||
*/
|
||||
def connectDataBeatCounter[S <: TileLinkChannel](inc: Bool, data: S, beat: UInt) = {
|
||||
val multi = data.hasMultibeatData()
|
||||
val (multi_cnt, multi_done) = Counter(inc && multi, data.tlDataBeats)
|
||||
val cnt = Mux(multi, multi_cnt, beat)
|
||||
val done = Mux(multi, multi_done, inc)
|
||||
(cnt, done)
|
||||
}
|
||||
|
||||
/** Counter for beats on outgoing [[chisel.DecoupledIO]] */
|
||||
def connectOutgoingDataBeatCounter[T <: TileLinkChannel](
|
||||
out: DecoupledIO[T],
|
||||
beat: UInt = UInt(0)): (UInt, Bool) =
|
||||
connectDataBeatCounter(out.fire(), out.bits, beat)
|
||||
|
||||
/** Returns done but not cnt. Use the addr_beat subbundle instead of cnt for beats on
|
||||
* incoming channels in case of network reordering.
|
||||
*/
|
||||
def connectIncomingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T]): Bool =
|
||||
connectDataBeatCounter(in.fire(), in.bits, UInt(0))._2
|
||||
|
||||
/** Counter for beats on incoming DecoupledIO[LogicalNetworkIO[]]s returns done */
|
||||
def connectIncomingDataBeatCounterWithHeader[T <: TileLinkChannel](in: DecoupledIO[LogicalNetworkIO[T]]): Bool =
|
||||
connectDataBeatCounter(in.fire(), in.bits.payload, UInt(0))._2
|
||||
|
||||
/** If the network might interleave beats from different messages, we need a Vec of counters,
|
||||
* one for every outstanding message id that might be interleaved.
|
||||
*
|
||||
* @param getId mapping from Message to counter id
|
||||
*/
|
||||
def connectIncomingDataBeatCountersWithHeader[T <: TileLinkChannel with HasClientTransactionId](
|
||||
in: DecoupledIO[LogicalNetworkIO[T]],
|
||||
entries: Int,
|
||||
getId: LogicalNetworkIO[T] => UInt): Vec[Bool] = {
|
||||
Vec((0 until entries).map { i =>
|
||||
connectDataBeatCounter(in.fire() && getId(in.bits) === UInt(i), in.bits.payload, UInt(0))._2
|
||||
})
|
||||
}
|
||||
|
||||
/** Provides counters on two channels, as well a meta-counter that tracks how many
|
||||
* messages have been sent over the up channel but not yet responded to over the down channel
|
||||
*
|
||||
* @param max max number of outstanding ups with no down
|
||||
* @param up outgoing channel
|
||||
* @param down incoming channel
|
||||
* @param beat overrides cnts on single-beat messages
|
||||
* @param track whether up's message should be tracked
|
||||
* @return a tuple containing whether their are outstanding messages, up's count,
|
||||
* up's done, down's count, down's done
|
||||
*/
|
||||
def connectTwoWayBeatCounter[T <: TileLinkChannel, S <: TileLinkChannel](
|
||||
max: Int,
|
||||
up: DecoupledIO[T],
|
||||
down: DecoupledIO[S],
|
||||
beat: UInt = UInt(0),
|
||||
track: T => Bool = (t: T) => Bool(true)): (Bool, UInt, Bool, UInt, Bool) = {
|
||||
val (up_idx, up_done) = connectDataBeatCounter(up.fire(), up.bits, beat)
|
||||
val (down_idx, down_done) = connectDataBeatCounter(down.fire(), down.bits, beat)
|
||||
val do_inc = up_done && track(up.bits)
|
||||
val do_dec = down_done
|
||||
val cnt = TwoWayCounter(do_inc, do_dec, max)
|
||||
(cnt > UInt(0), up_idx, up_done, down_idx, down_done)
|
||||
}
|
||||
}
|
||||
|
||||
class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = new ClientTileLinkIO().flip
|
||||
val out = new ClientUncachedTileLinkIO
|
||||
}
|
||||
|
||||
def needsRoqEnq(channel: HasTileLinkData): Bool =
|
||||
!channel.hasMultibeatData() || channel.addr_beat === UInt(0)
|
||||
|
||||
def needsRoqDeq(channel: HasTileLinkData): Bool =
|
||||
!channel.hasMultibeatData() || channel.addr_beat === UInt(tlDataBeats - 1)
|
||||
|
||||
val acqArb = Module(new LockingRRArbiter(new Acquire, 2, tlDataBeats,
|
||||
Some((acq: Acquire) => acq.hasMultibeatData())))
|
||||
|
||||
val acqRoq = Module(new ReorderQueue(
|
||||
Bool(), tlClientXactIdBits, tlMaxClientsPerPort))
|
||||
|
||||
val relRoq = Module(new ReorderQueue(
|
||||
Bool(), tlClientXactIdBits, tlMaxClientsPerPort))
|
||||
|
||||
val iacq = io.in.acquire.bits
|
||||
val irel = io.in.release.bits
|
||||
val ognt = io.out.grant.bits
|
||||
|
||||
val acq_roq_enq = needsRoqEnq(iacq)
|
||||
val rel_roq_enq = needsRoqEnq(irel)
|
||||
|
||||
val acq_roq_ready = !acq_roq_enq || acqRoq.io.enq.ready
|
||||
val rel_roq_ready = !rel_roq_enq || relRoq.io.enq.ready
|
||||
|
||||
val acq_helper = DecoupledHelper(
|
||||
io.in.acquire.valid,
|
||||
acq_roq_ready,
|
||||
acqArb.io.in(0).ready)
|
||||
|
||||
val rel_helper = DecoupledHelper(
|
||||
io.in.release.valid,
|
||||
rel_roq_ready,
|
||||
acqArb.io.in(1).ready)
|
||||
|
||||
acqRoq.io.enq.valid := acq_helper.fire(acq_roq_ready, acq_roq_enq)
|
||||
acqRoq.io.enq.bits.data := iacq.isBuiltInType()
|
||||
acqRoq.io.enq.bits.tag := iacq.client_xact_id
|
||||
|
||||
acqArb.io.in(0).valid := acq_helper.fire(acqArb.io.in(0).ready)
|
||||
acqArb.io.in(0).bits := Acquire(
|
||||
is_builtin_type = Bool(true),
|
||||
a_type = Mux(iacq.isBuiltInType(),
|
||||
iacq.a_type, Acquire.getBlockType),
|
||||
client_xact_id = iacq.client_xact_id,
|
||||
addr_block = iacq.addr_block,
|
||||
addr_beat = iacq.addr_beat,
|
||||
data = iacq.data,
|
||||
union = Mux(iacq.isBuiltInType(),
|
||||
iacq.union, Cat(MT_Q, M_XRD, Bool(true))))
|
||||
io.in.acquire.ready := acq_helper.fire(io.in.acquire.valid)
|
||||
|
||||
relRoq.io.enq.valid := rel_helper.fire(rel_roq_ready, rel_roq_enq)
|
||||
relRoq.io.enq.bits.data := irel.isVoluntary()
|
||||
relRoq.io.enq.bits.tag := irel.client_xact_id
|
||||
|
||||
acqArb.io.in(1).valid := rel_helper.fire(acqArb.io.in(1).ready)
|
||||
acqArb.io.in(1).bits := PutBlock(
|
||||
client_xact_id = irel.client_xact_id,
|
||||
addr_block = irel.addr_block,
|
||||
addr_beat = irel.addr_beat,
|
||||
data = irel.data,
|
||||
wmask = Acquire.fullWriteMask)
|
||||
io.in.release.ready := rel_helper.fire(io.in.release.valid)
|
||||
|
||||
io.out.acquire <> acqArb.io.out
|
||||
|
||||
acqRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt)
|
||||
acqRoq.io.deq.tag := ognt.client_xact_id
|
||||
|
||||
relRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt)
|
||||
relRoq.io.deq.tag := ognt.client_xact_id
|
||||
|
||||
val gnt_builtin = acqRoq.io.deq.data
|
||||
val gnt_voluntary = relRoq.io.deq.data
|
||||
|
||||
val acq_grant = Grant(
|
||||
is_builtin_type = gnt_builtin,
|
||||
g_type = Mux(gnt_builtin, ognt.g_type, tlCoh.getExclusiveGrantType),
|
||||
client_xact_id = ognt.client_xact_id,
|
||||
manager_xact_id = ognt.manager_xact_id,
|
||||
addr_beat = ognt.addr_beat,
|
||||
data = ognt.data)
|
||||
|
||||
val rel_grant = Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Mux(gnt_voluntary, Grant.voluntaryAckType, ognt.g_type),
|
||||
client_xact_id = ognt.client_xact_id,
|
||||
manager_xact_id = ognt.manager_xact_id,
|
||||
addr_beat = ognt.addr_beat,
|
||||
data = ognt.data)
|
||||
|
||||
io.in.grant.valid := io.out.grant.valid
|
||||
io.in.grant.bits := Mux(acqRoq.io.deq.matches, acq_grant, rel_grant)
|
||||
io.out.grant.ready := io.in.grant.ready
|
||||
|
||||
io.in.probe.valid := Bool(false)
|
||||
}
|
||||
|
||||
class NastiIOTileLinkIOConverterInfo(implicit p: Parameters) extends TLBundle()(p) {
|
||||
val addr_beat = UInt(width = tlBeatAddrBits)
|
||||
val byteOff = UInt(width = tlByteAddrBits)
|
||||
val subblock = Bool()
|
||||
}
|
||||
|
||||
class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
|
||||
with HasNastiParameters {
|
||||
val io = new Bundle {
|
||||
val tl = new ClientUncachedTileLinkIO().flip
|
||||
val nasti = new NastiIO
|
||||
}
|
||||
|
||||
private def opSizeToXSize(ops: UInt) = MuxLookup(ops, UInt("b111"), Seq(
|
||||
MT_B -> UInt(0),
|
||||
MT_BU -> UInt(0),
|
||||
MT_H -> UInt(1),
|
||||
MT_HU -> UInt(1),
|
||||
MT_W -> UInt(2),
|
||||
MT_D -> UInt(3),
|
||||
MT_Q -> UInt(log2Up(tlDataBytes))))
|
||||
|
||||
val dataBits = tlDataBits*tlDataBeats
|
||||
require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
|
||||
require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
|
||||
require(tlClientXactIdBits <= nastiXIdBits, "NastiIO converter is going truncate tags: " + tlClientXactIdBits + " > " + nastiXIdBits)
|
||||
|
||||
val has_data = io.tl.acquire.bits.hasData()
|
||||
|
||||
val is_subblock = io.tl.acquire.bits.isSubBlockType()
|
||||
val is_multibeat = io.tl.acquire.bits.hasMultibeatData()
|
||||
val (tl_cnt_out, tl_wrap_out) = Counter(
|
||||
io.tl.acquire.fire() && is_multibeat, tlDataBeats)
|
||||
|
||||
val get_valid = io.tl.acquire.valid && !has_data
|
||||
val put_valid = io.tl.acquire.valid && has_data
|
||||
|
||||
// Reorder queue saves extra information needed to send correct
|
||||
// grant back to TL client
|
||||
val roq = Module(new ReorderQueue(
|
||||
new NastiIOTileLinkIOConverterInfo,
|
||||
nastiRIdBits, tlMaxClientsPerPort))
|
||||
|
||||
// For Get/GetBlock, make sure Reorder queue can accept new entry
|
||||
val get_helper = DecoupledHelper(
|
||||
get_valid,
|
||||
roq.io.enq.ready,
|
||||
io.nasti.ar.ready)
|
||||
|
||||
val w_inflight = Reg(init = Bool(false))
|
||||
|
||||
// For Put/PutBlock, make sure aw and w channel are both ready before
|
||||
// we send the first beat
|
||||
val aw_ready = w_inflight || io.nasti.aw.ready
|
||||
val put_helper = DecoupledHelper(
|
||||
put_valid,
|
||||
aw_ready,
|
||||
io.nasti.w.ready)
|
||||
|
||||
val (nasti_cnt_out, nasti_wrap_out) = Counter(
|
||||
io.nasti.r.fire() && !roq.io.deq.data.subblock, tlDataBeats)
|
||||
|
||||
roq.io.enq.valid := get_helper.fire(roq.io.enq.ready)
|
||||
roq.io.enq.bits.tag := io.nasti.ar.bits.id
|
||||
roq.io.enq.bits.data.addr_beat := io.tl.acquire.bits.addr_beat
|
||||
roq.io.enq.bits.data.byteOff := io.tl.acquire.bits.addr_byte()
|
||||
roq.io.enq.bits.data.subblock := is_subblock
|
||||
roq.io.deq.valid := io.nasti.r.fire() && (nasti_wrap_out || roq.io.deq.data.subblock)
|
||||
roq.io.deq.tag := io.nasti.r.bits.id
|
||||
|
||||
// Decompose outgoing TL Acquires into Nasti address and data channels
|
||||
io.nasti.ar.valid := get_helper.fire(io.nasti.ar.ready)
|
||||
io.nasti.ar.bits := NastiReadAddressChannel(
|
||||
id = io.tl.acquire.bits.client_xact_id,
|
||||
addr = io.tl.acquire.bits.full_addr(),
|
||||
size = Mux(is_subblock,
|
||||
opSizeToXSize(io.tl.acquire.bits.op_size()),
|
||||
UInt(log2Ceil(tlDataBytes))),
|
||||
len = Mux(is_subblock, UInt(0), UInt(tlDataBeats - 1)))
|
||||
|
||||
io.nasti.aw.valid := put_helper.fire(aw_ready, !w_inflight)
|
||||
io.nasti.aw.bits := NastiWriteAddressChannel(
|
||||
id = io.tl.acquire.bits.client_xact_id,
|
||||
addr = io.tl.acquire.bits.full_addr(),
|
||||
size = UInt(log2Ceil(tlDataBytes)),
|
||||
len = Mux(is_multibeat, UInt(tlDataBeats - 1), UInt(0)))
|
||||
|
||||
io.nasti.w.valid := put_helper.fire(io.nasti.w.ready)
|
||||
io.nasti.w.bits := NastiWriteDataChannel(
|
||||
data = io.tl.acquire.bits.data,
|
||||
strb = io.tl.acquire.bits.wmask(),
|
||||
last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock))
|
||||
|
||||
io.tl.acquire.ready := Mux(has_data,
|
||||
put_helper.fire(put_valid),
|
||||
get_helper.fire(get_valid))
|
||||
|
||||
when (!w_inflight && io.tl.acquire.fire() && is_multibeat) {
|
||||
w_inflight := Bool(true)
|
||||
}
|
||||
|
||||
when (w_inflight) {
|
||||
when (tl_wrap_out) { w_inflight := Bool(false) }
|
||||
}
|
||||
|
||||
// Aggregate incoming NASTI responses into TL Grants
|
||||
val (tl_cnt_in, tl_wrap_in) = Counter(
|
||||
io.tl.grant.fire() && io.tl.grant.bits.hasMultibeatData(), tlDataBeats)
|
||||
val gnt_arb = Module(new Arbiter(new GrantToDst, 2))
|
||||
io.tl.grant <> gnt_arb.io.out
|
||||
|
||||
val r_aligned_data = Mux(roq.io.deq.data.subblock,
|
||||
io.nasti.r.bits.data << Cat(roq.io.deq.data.byteOff, UInt(0, 3)),
|
||||
io.nasti.r.bits.data)
|
||||
|
||||
gnt_arb.io.in(0).valid := io.nasti.r.valid
|
||||
io.nasti.r.ready := gnt_arb.io.in(0).ready
|
||||
gnt_arb.io.in(0).bits := Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Mux(roq.io.deq.data.subblock,
|
||||
Grant.getDataBeatType, Grant.getDataBlockType),
|
||||
client_xact_id = io.nasti.r.bits.id,
|
||||
manager_xact_id = UInt(0),
|
||||
addr_beat = Mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in),
|
||||
data = r_aligned_data)
|
||||
|
||||
gnt_arb.io.in(1).valid := io.nasti.b.valid
|
||||
io.nasti.b.ready := gnt_arb.io.in(1).ready
|
||||
gnt_arb.io.in(1).bits := Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Grant.putAckType,
|
||||
client_xact_id = io.nasti.b.bits.id,
|
||||
manager_xact_id = UInt(0),
|
||||
addr_beat = UInt(0),
|
||||
data = Bits(0))
|
||||
|
||||
assert(!io.nasti.r.valid || io.nasti.r.bits.resp === UInt(0), "NASTI read error")
|
||||
assert(!io.nasti.b.valid || io.nasti.b.bits.resp === UInt(0), "NASTI write error")
|
||||
}
|
||||
|
||||
class TileLinkIONarrower(innerTLId: String, outerTLId: String)
|
||||
(implicit p: Parameters) extends TLModule()(p) {
|
||||
|
||||
val innerParams = p(TLKey(innerTLId))
|
||||
val outerParams = p(TLKey(outerTLId))
|
||||
val innerDataBeats = innerParams.dataBeats
|
||||
val innerDataBits = innerParams.dataBitsPerBeat
|
||||
val innerWriteMaskBits = innerParams.writeMaskBits
|
||||
val innerByteAddrBits = log2Up(innerWriteMaskBits)
|
||||
val outerDataBeats = outerParams.dataBeats
|
||||
val outerDataBits = outerParams.dataBitsPerBeat
|
||||
val outerWriteMaskBits = outerParams.writeMaskBits
|
||||
val outerByteAddrBits = log2Up(outerWriteMaskBits)
|
||||
val outerBeatAddrBits = log2Up(outerDataBeats)
|
||||
val outerBlockOffset = outerBeatAddrBits + outerByteAddrBits
|
||||
val outerMaxClients = outerParams.maxClientsPerPort
|
||||
val outerIdBits = log2Up(outerParams.maxClientXacts * outerMaxClients)
|
||||
|
||||
require(outerDataBeats >= innerDataBeats)
|
||||
require(outerDataBeats % innerDataBeats == 0)
|
||||
require(outerDataBits <= innerDataBits)
|
||||
require(outerDataBits * outerDataBeats == innerDataBits * innerDataBeats)
|
||||
|
||||
val factor = outerDataBeats / innerDataBeats
|
||||
|
||||
val io = new Bundle {
|
||||
val in = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => innerTLId})).flip
|
||||
val out = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => outerTLId}))
|
||||
}
|
||||
|
||||
if (factor > 1) {
|
||||
val iacq = io.in.acquire.bits
|
||||
val ognt = io.out.grant.bits
|
||||
|
||||
val stretch = iacq.a_type === Acquire.putBlockType
|
||||
val shrink = iacq.a_type === Acquire.getBlockType
|
||||
val smallput = iacq.a_type === Acquire.putType
|
||||
val smallget = iacq.a_type === Acquire.getType
|
||||
|
||||
val acq_data_buffer = Reg(UInt(width = innerDataBits))
|
||||
val acq_wmask_buffer = Reg(UInt(width = innerWriteMaskBits))
|
||||
val acq_client_id = Reg(iacq.client_xact_id)
|
||||
val acq_addr_block = Reg(iacq.addr_block)
|
||||
val acq_addr_beat = Reg(iacq.addr_beat)
|
||||
val oacq_ctr = Counter(factor)
|
||||
|
||||
// this part of the address shifts from the inner byte address
|
||||
// to the outer beat address
|
||||
val readshift = iacq.full_addr()(innerByteAddrBits - 1, outerByteAddrBits)
|
||||
val outer_beat_addr = iacq.full_addr()(outerBlockOffset - 1, outerByteAddrBits)
|
||||
val outer_byte_addr = iacq.full_addr()(outerByteAddrBits - 1, 0)
|
||||
|
||||
val mask_chunks = Vec.tabulate(factor) { i =>
|
||||
val lsb = i * outerWriteMaskBits
|
||||
val msb = (i + 1) * outerWriteMaskBits - 1
|
||||
iacq.wmask()(msb, lsb)
|
||||
}
|
||||
|
||||
val data_chunks = Vec.tabulate(factor) { i =>
|
||||
val lsb = i * outerDataBits
|
||||
val msb = (i + 1) * outerDataBits - 1
|
||||
iacq.data(msb, lsb)
|
||||
}
|
||||
|
||||
val beat_sel = Cat(mask_chunks.map(mask => mask.orR).reverse)
|
||||
|
||||
val smallput_data = Mux1H(beat_sel, data_chunks)
|
||||
val smallput_wmask = Mux1H(beat_sel, mask_chunks)
|
||||
val smallput_beat = Cat(iacq.addr_beat, PriorityEncoder(beat_sel))
|
||||
|
||||
assert(!io.in.acquire.valid || !smallput || PopCount(beat_sel) <= UInt(1),
|
||||
"Can't perform Put wider than outer width")
|
||||
|
||||
val read_size_ok = MuxLookup(iacq.op_size(), Bool(false), Seq(
|
||||
MT_B -> Bool(true),
|
||||
MT_BU -> Bool(true),
|
||||
MT_H -> Bool(outerDataBits >= 16),
|
||||
MT_HU -> Bool(outerDataBits >= 16),
|
||||
MT_W -> Bool(outerDataBits >= 32),
|
||||
MT_D -> Bool(outerDataBits >= 64),
|
||||
MT_Q -> Bool(false)))
|
||||
|
||||
assert(!io.in.acquire.valid || !smallget || read_size_ok,
|
||||
"Can't perform Get wider than outer width")
|
||||
|
||||
val outerConfig = p.alterPartial({ case TLId => outerTLId })
|
||||
val innerConfig = p.alterPartial({ case TLId => innerTLId })
|
||||
|
||||
val get_block_acquire = GetBlock(
|
||||
client_xact_id = iacq.client_xact_id,
|
||||
addr_block = iacq.addr_block,
|
||||
alloc = iacq.allocate())(outerConfig)
|
||||
|
||||
val put_block_acquire = PutBlock(
|
||||
client_xact_id = acq_client_id,
|
||||
addr_block = acq_addr_block,
|
||||
addr_beat = if (factor > 1)
|
||||
Cat(acq_addr_beat, oacq_ctr.value)
|
||||
else acq_addr_beat,
|
||||
data = acq_data_buffer(outerDataBits - 1, 0),
|
||||
wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))(outerConfig)
|
||||
|
||||
val get_acquire = Get(
|
||||
client_xact_id = iacq.client_xact_id,
|
||||
addr_block = iacq.addr_block,
|
||||
addr_beat = outer_beat_addr,
|
||||
addr_byte = outer_byte_addr,
|
||||
operand_size = iacq.op_size(),
|
||||
alloc = iacq.allocate())(outerConfig)
|
||||
|
||||
val put_acquire = Put(
|
||||
client_xact_id = iacq.client_xact_id,
|
||||
addr_block = iacq.addr_block,
|
||||
addr_beat = smallput_beat,
|
||||
data = smallput_data,
|
||||
wmask = Some(smallput_wmask))(outerConfig)
|
||||
|
||||
val sending_put = Reg(init = Bool(false))
|
||||
|
||||
val pass_valid = io.in.acquire.valid && !stretch && !smallget
|
||||
val smallget_valid = smallget && io.in.acquire.valid
|
||||
|
||||
val smallget_roq = Module(new ReorderQueue(
|
||||
readshift, outerIdBits, outerMaxClients))
|
||||
|
||||
val smallget_helper = DecoupledHelper(
|
||||
smallget_valid,
|
||||
smallget_roq.io.enq.ready,
|
||||
io.out.acquire.ready)
|
||||
|
||||
smallget_roq.io.enq.valid := smallget_helper.fire(
|
||||
smallget_roq.io.enq.ready, !sending_put)
|
||||
smallget_roq.io.enq.bits.data := readshift
|
||||
smallget_roq.io.enq.bits.tag := iacq.client_xact_id
|
||||
|
||||
io.out.acquire.bits := MuxBundle(iacq, Seq(
|
||||
(sending_put, put_block_acquire),
|
||||
(shrink, get_block_acquire),
|
||||
(smallput, put_acquire),
|
||||
(smallget, get_acquire)))
|
||||
io.out.acquire.valid := sending_put || pass_valid ||
|
||||
smallget_helper.fire(io.out.acquire.ready)
|
||||
io.in.acquire.ready := !sending_put && (stretch ||
|
||||
(!smallget && io.out.acquire.ready) ||
|
||||
smallget_helper.fire(smallget_valid))
|
||||
|
||||
when (io.in.acquire.fire() && stretch) {
|
||||
acq_data_buffer := iacq.data
|
||||
acq_wmask_buffer := iacq.wmask()
|
||||
acq_client_id := iacq.client_xact_id
|
||||
acq_addr_block := iacq.addr_block
|
||||
acq_addr_beat := iacq.addr_beat
|
||||
sending_put := Bool(true)
|
||||
}
|
||||
|
||||
when (sending_put && io.out.acquire.ready) {
|
||||
acq_data_buffer := acq_data_buffer >> outerDataBits
|
||||
acq_wmask_buffer := acq_wmask_buffer >> outerWriteMaskBits
|
||||
when (oacq_ctr.inc()) { sending_put := Bool(false) }
|
||||
}
|
||||
|
||||
val ognt_block = ognt.hasMultibeatData()
|
||||
val gnt_data_buffer = Reg(Vec(factor, UInt(width = outerDataBits)))
|
||||
val gnt_client_id = Reg(ognt.client_xact_id)
|
||||
val gnt_manager_id = Reg(ognt.manager_xact_id)
|
||||
|
||||
val ignt_ctr = Counter(innerDataBeats)
|
||||
val ognt_ctr = Counter(factor)
|
||||
val sending_get = Reg(init = Bool(false))
|
||||
|
||||
val get_block_grant = Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Grant.getDataBlockType,
|
||||
client_xact_id = gnt_client_id,
|
||||
manager_xact_id = gnt_manager_id,
|
||||
addr_beat = ignt_ctr.value,
|
||||
data = gnt_data_buffer.toBits)(innerConfig)
|
||||
|
||||
val smallget_grant = ognt.g_type === Grant.getDataBeatType
|
||||
val get_grant_shift = Cat(smallget_roq.io.deq.data,
|
||||
UInt(0, outerByteAddrBits + 3))
|
||||
|
||||
smallget_roq.io.deq.valid := io.out.grant.fire() && smallget_grant
|
||||
smallget_roq.io.deq.tag := ognt.client_xact_id
|
||||
|
||||
val get_grant = Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = Grant.getDataBeatType,
|
||||
client_xact_id = ognt.client_xact_id,
|
||||
manager_xact_id = ognt.manager_xact_id,
|
||||
addr_beat = ognt.addr_beat >> UInt(log2Up(factor)),
|
||||
data = ognt.data << get_grant_shift)(innerConfig)
|
||||
|
||||
io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
|
||||
io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)
|
||||
io.in.grant.bits := MuxBundle(ognt, Seq(
|
||||
sending_get -> get_block_grant,
|
||||
smallget_grant -> get_grant))
|
||||
|
||||
when (io.out.grant.valid && ognt_block && !sending_get) {
|
||||
gnt_data_buffer(ognt_ctr.value) := ognt.data
|
||||
when (ognt_ctr.inc()) {
|
||||
gnt_client_id := ognt.client_xact_id
|
||||
gnt_manager_id := ognt.manager_xact_id
|
||||
sending_get := Bool(true)
|
||||
}
|
||||
}
|
||||
|
||||
when (io.in.grant.ready && sending_get) {
|
||||
ignt_ctr.inc()
|
||||
sending_get := Bool(false)
|
||||
}
|
||||
} else { io.out <> io.in }
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user