riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 12f0369e6e Simplify divide early out circuitry 2013-10-29 13:20:40 -07:00
Andrew Waterman b44dafbdca Simplify branch offset mux 2013-10-29 13:20:40 -07:00
Andrew Waterman 23f7bab4f3 Reduce FMA pipeline depths 
FMA QoR has improved enough to allow this change.
 2013-10-29 13:20:40 -07:00
Andrew Waterman ea9d0b771e remove aborts; simplify probes 2013-03-19 15:29:40 -07:00
Andrew Waterman 78868f6075 add config option to trade mul/div area for speed 2013-01-06 03:47:17 -08:00
Andrew Waterman ce9f4881d2 remove broken multiplier early out 2013-01-06 03:47:00 -08:00
Andrew Waterman 05f19b21d0 merge multiplier and divider 2012-12-12 02:22:47 -08:00
Andrew Waterman c921fc34a9 merge ALU left and right shifters 2012-12-12 02:22:34 -08:00
Andrew Waterman f5c53ce35d add ecc support to d$ data rams 
i haven't injected errors yet; it may well be incorrect.
 2012-12-11 15:58:53 -08:00
Andrew Waterman 3f59e439ef fix d$ tag raw hazard 2012-12-07 15:14:20 -08:00
Andrew Waterman e9752f1d72 pipeline host pcr access 2012-12-06 14:22:07 -08:00
Andrew Waterman 4dda38204f fix d$ reset bug 2012-12-06 03:13:22 -08:00
Andrew Waterman 290d3d226c fix AMO and store bypass bugs 
thanks, torture tester
 2012-12-06 02:07:52 -08:00
Andrew Waterman 4608660f6e torture revealed a couple bugs 
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
 2012-12-04 05:57:53 -08:00
Andrew Waterman 90cae54ac4 fix D$ read/write concurrency bug 2012-11-27 02:42:27 -08:00
Andrew Waterman 9c857b83f0 refactor PCR file 2012-11-27 01:28:06 -08:00
Andrew Waterman 64674d4d39 clean up PTW and support PADDR_BITS < VADDR_BITS 2012-11-26 20:38:45 -08:00
Andrew Waterman 608f65e716 don't wastefully read 2x the bits from D$ RAMs 2012-11-26 20:34:30 -08:00
Andrew Waterman 352bb464b5 clock gate X/M and M/W store data registers 2012-11-26 20:33:41 -08:00
Andrew Waterman 8a6ff5f9aa fix D$ writeback bug 
I swear I did this last week... perhaps I am finally losing it!
 2012-11-25 19:46:48 -08:00
Andrew Waterman de2f28193a get rid of more global constants 2012-11-25 04:24:25 -08:00
Andrew Waterman c036cdc1ea add option for 2-cycle load-use delay 2012-11-24 22:01:08 -08:00
Andrew Waterman b514c7b725 clean up I$ parity code 2012-11-24 22:00:43 -08:00
Andrew Waterman 55082e45c4 add AVec, which automatically infers element type 
should consider modifying Vec as such
 2012-11-24 18:19:28 -08:00
Andrew Waterman 2b26082132 use 1r1w ram for tags; merge tags & permissions 
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
 2012-11-20 04:09:26 -08:00
Andrew Waterman 72f94d1141 fix virtual address sign extension detection 2012-11-20 04:06:57 -08:00
Andrew Waterman 30038bda8a bypass stores to subsequent loads 
since we handle subword stores as RMW operations, this occurs frequently
 2012-11-20 01:33:32 -08:00
Andrew Waterman 29bc361d6c remove global constants; disentangle hwacha a bit 2012-11-17 17:24:08 -08:00
Andrew Waterman 5a7777fe4d clock gate integer datapath more aggressively 2012-11-17 06:48:44 -08:00
Andrew Waterman cc067026a2 pipeline D$ response -> FPU regfile 2012-11-17 06:48:11 -08:00
Andrew Waterman e68b039133 fix misc. D$ control bugs 2012-11-17 06:47:27 -08:00
Andrew Waterman dad7b71062 provide cmd/addr with cache response 2012-11-16 21:26:12 -08:00
Andrew Waterman cb8ac73045 provide store data with cache response 2012-11-16 21:15:13 -08:00
Andrew Waterman 9e010beffe fix D$ refill bug 2012-11-16 21:05:29 -08:00
Andrew Waterman 8dce89703a new D$ with better QoR and AMO pipelining 
Vector unit is disabled because nack handling needs to be fixed.
 2012-11-16 02:39:33 -08:00
Andrew Waterman a90a1790a5 improve tlb qor 2012-11-16 01:59:38 -08:00
Andrew Waterman ff8c736d94 move icache invalidate out of request bundle 2012-11-16 01:55:45 -08:00
Andrew Waterman 6d10115b19 fix D$ tag width 2012-11-15 16:46:39 -08:00
Andrew Waterman 4d1ca8ba3a remove more global consts; refactor DTLBs 
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
 2012-11-06 08:13:44 -08:00
Andrew Waterman e76892f758 remove more global constants 2012-11-06 02:55:45 -08:00
Andrew Waterman c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Andrew Waterman 5b20ed71be move rd=0 check into bypass logic 
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
 2012-11-05 01:30:57 -08:00
Andrew Waterman 5e103054fd fix bug in quine mccluskey 2012-11-05 00:28:25 -08:00
Andrew Waterman e9eca6a95d refactor I$ config; remove Top class 2012-11-04 16:59:36 -08:00
Andrew Waterman 7380c9fe60 aggressively clock gate int and fp datapaths 2012-11-04 16:40:14 -08:00
Andrew Waterman bd2d61de03 use 8T SRAM for I$; gate clock more aggressively 2012-11-04 16:39:25 -08:00
Andrew Waterman fedee6c67d add generic error correcting codes 2012-10-30 01:03:47 -07:00
Andrew Waterman 5773cbb68a rejigger htif to use UncoreConfiguration 2012-10-18 17:26:03 -07:00
Andrew Waterman b9a2af697d turn off HAVE_VEC as it's currently broken 
the new I$/frontend needs to be integrated
 2012-10-16 07:38:19 -07:00
Andrew Waterman 0a640f2cc6 make DecodeLogic deterministic (hopefully) 2012-10-16 04:51:21 -07:00
Andrew Waterman 5821900329 don't refetch from I$ if on same 16B block 2012-10-16 02:24:38 -07:00
Andrew Waterman b955985b38 improve divider QoR 2012-10-16 02:24:38 -07:00
Andrew Waterman 197154c485 use BTB for JALR 2012-10-16 02:24:37 -07:00
Andrew Waterman fc648d13a1 remove old Mux1H; add implicit conversions 2012-10-16 02:24:37 -07:00
Andrew Waterman 661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00
Andrew Waterman fcd69dba98 add optional early-out to mul/div 2012-10-16 02:24:37 -07:00
Andrew Waterman 27ddff1adb simplify and improve multiplier 2012-10-16 02:24:37 -07:00
Andrew Waterman ed8cc4a1cf eliminate D$ probe->WB critical path 2012-10-04 09:05:14 -07:00
Andrew Waterman 897a4e349b fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman e9c35b4923 ameliorate DTLB kill->rdy critical path 2012-08-06 17:05:05 -07:00
Andrew Waterman b94e6915ab refactor IPIs; use new tohost/fromhost protocol 2012-08-03 19:00:34 -07:00
Andrew Waterman 6510f020c7 fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman e3726c4db0 fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman def913096e pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman 3a8f3e0de5 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman be4fa936dd fix PriorityEncoderOH bug 2012-07-30 18:28:54 -07:00
Andrew Waterman 130fa95ed6 expand HTIF's PCR register space 2012-07-27 14:52:39 -07:00
Andrew Waterman 9c50621a19 remove chip-specific uncore gunk 2012-07-26 03:26:52 -07:00
Andrew Waterman a5bea4364f memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman 177dbdadd9 merge HTIF port and backup memory port 2012-07-25 00:18:02 -07:00
Andrew Waterman a21c355114 fix htif split request/response 2012-07-23 17:15:16 -07:00
Andrew Waterman 938effc053 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman f42c6afed2 decouple all interfaces between tile and top 
also, add an "incoherent" bit to tilelink to indicate no probes needed
 2012-07-17 22:55:40 -07:00
Andrew Waterman 4e44ed7400 allow back pressure on IPI requests 2012-07-17 22:55:40 -07:00
Andrew Waterman 5035374f36 update to new chisel 2012-07-08 17:59:41 -07:00
Andrew Waterman 4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Andrew Waterman 943b6d0616 remove debug println 2012-06-06 02:48:48 -07:00
Andrew Waterman 7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Andrew Waterman faee45bf4c fix setpcr/clearpcr not writing rd 2012-05-21 07:25:35 -07:00
Andrew Waterman a2f6d01c1b add programmable coreid register 2012-05-09 03:09:22 -07:00
Andrew Waterman e0e1cd5d32 add IPIs and an IPI test 
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
 2012-05-08 22:58:00 -07:00
Andrew Waterman b851f1b34c support maximum-MTU HTIF packets 2012-05-03 21:11:43 -07:00
Andrew Waterman 171c87002e reduce HTIF clock divider for now 2012-05-03 04:21:11 -07:00
Andrew Waterman e1f9dc2c1f generalize page table walker 
also, don't instantiate vitlb when !HAVE_VEC
 2012-05-03 02:29:09 -07:00
Andrew Waterman 2d4e5d3813 fix pseudo-LRU verilog generation bug 2012-05-02 19:31:31 -07:00
Andrew Waterman 65ff397122 improved instruction decoding 
it now makes use of don't-cares by performing logic minimization
 2012-05-01 20:16:36 -07:00
Andrew Waterman 4cfa6cd9a8 force Top.main's return type to Unit 2012-05-01 19:55:16 -07:00
Andrew Waterman 5819beed64 use parameterized FP units 2012-05-01 01:25:43 -07:00
Andrew Waterman eafdffe125 simplify page table walker; speed up emulator 2012-05-01 01:24:36 -07:00
Andrew Waterman c13d3e6f88 fix probe tag read-modify-write atomicity violation 2012-04-26 02:29:31 -07:00
Andrew Waterman 66f86a2194 use pseudo-LRU replacement for TLBs 2012-04-26 02:29:30 -07:00
Andrew Waterman a0378c5d2f remove faulting TLB entry after page fault 
this vastly reduces the frequency with which the TLB must be flushed
 2012-04-26 02:29:30 -07:00
Andrew Waterman 6d8fc74378 fix DTLB permissions bug 2012-04-26 02:29:30 -07:00
Andrew Waterman fb4408b150 fix AMO replay/coherence deadlock 2012-04-15 22:56:02 -07:00
Andrew Waterman 724735f13f fix writeback bug 2012-04-13 03:16:48 -07:00
Andrew Waterman 00d934cfac fix coherence bugs in cache 2012-04-12 21:57:37 -07:00
Andrew Waterman c0ec3794bf coherence mostly works now 2012-04-10 02:22:45 -07:00
Andrew Waterman aee9378712 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Andrew Waterman 7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Andrew Waterman a09e8d1c55 remove I$ prefetcher for now 
there's a bug in it, and I don't have time to fix it at the moment.
 2012-03-27 15:43:56 -07:00