riscv/sifive-blocks
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Author SHA1 Message Date
Yunsup Lee
4cb2f8af17 mockaon: rename pads to pins 2017-07-25 15:02:22 -07:00
Megan Wachs
aa6d911c26 Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant 2017-07-25 08:36:28 -07:00
Megan Wachs
2139ab0d98 Merge remote-tracking branch 'origin/master' into typed_pad_ctrl 2017-07-25 07:05:22 -07:00
Yunsup Lee
5e51e1e931 uart: use PeripheryBusParams.frequency to calculate default divisor (#28) 2017-07-25 00:56:22 -07:00
Megan Wachs
0a80d1987d Merge remote-tracking branch 'origin/master' into typed_pad_ctrl 2017-07-24 10:11:52 -07:00
Henry Cook
9ae6413273 periphery: peripherals now in coreplex (#26) 
* periphery: peripherals now in coreplex

* use fromAsyncFIFOMaster
 2017-07-23 08:31:44 -07:00
Megan Wachs
2bad829e6e gpio: Add missing file 2017-07-20 14:53:34 -07:00
Megan Wachs
06f0d20742 Add missing cloneType methods to pin bundles 2017-07-20 11:36:31 -07:00
Megan Wachs
00086c26e6 i2c: Remove pluralization on the bundle name, i2c not i2cs 2017-07-20 10:53:44 -07:00
Megan Wachs
ef4f2ed888 Remove pluralization on interface names. Require clocks and resets explicitly when necessary 2017-07-19 14:51:50 -07:00
Megan Wachs
4d74e8f67f Make it possible to adjust the type of pad controls used, 
and seperate out some of the "GPIO Peripheral" from "Pin Control"
 2017-07-19 08:01:42 -07:00
Henry Cook
fb9dd31374 Refactor package hierarchy. (#25) 2017-07-07 10:48:57 -07:00
Wesley W. Terpstra
66b2fd11bd vc707 axi enhancements (#24) 
1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)
 2017-06-30 12:36:33 -07:00
Wesley W. Terpstra
886680af49 mig: fix MemoryDevice to use 'reg' properly 2017-06-29 13:41:30 -07:00
Wesley W. Terpstra
a8e20f447c spi: include mem region (#23) 2017-06-28 17:46:45 -07:00
Wesley W. Terpstra
3d8c502fce diplomacy: add reg-names to devices (#22) 2017-06-28 17:45:18 -07:00
Megan Wachs
2154e9eb3f gpio: Make IOF optional (#21) 
* gpio: Make IOF optional

* IOF: Make the default false
 2017-06-19 12:41:38 -07:00
Henry Cook
473464eaa9 make some base bundle classes easier to clone (#20) 2017-06-14 19:47:56 -07:00
Wesley W. Terpstra
90d3931f5a spi: add dts ranges field for memory mapped spi (#19) 2017-06-14 17:06:55 -07:00
Henry Cook
dacca7e7b1 Merge pull request #18 from sifive/lazy-raw-module-imp 
periphery: convert bundle traits
 2017-06-13 15:52:11 -07:00
Megan Wachs
8bfda68858 More Peripheral-to-pins cleanups 2017-06-13 11:00:29 -07:00
Megan Wachs
b3f656affe UART: actually return the pins, not just the module. We should do this for the other peripherals as well 2017-06-12 18:08:35 -07:00
Megan Wachs
b06b80dccd GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. 2017-06-12 17:53:51 -07:00
Megan Wachs
7c118790cb GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. 2017-06-12 17:53:08 -07:00
Henry Cook
d4bb8a77ea periphery: convert periphery bundle traits to work with system-level multi-io module 2017-06-12 16:57:47 -07:00
Megan Wachs
27b00e177c Merge pull request #17 from sifive/peripheral_options 
Make more peripherals "listable" to allow for 0 or more
 2017-06-09 22:07:43 -07:00
Megan Wachs
79f64de12c peripheral_options: Actually compiles 2017-06-09 13:53:22 -07:00
Megan Wachs
29226701a8 SPIFlash: make it listable 2017-06-08 16:29:01 -07:00
Megan Wachs
c89f163c0d GPIO: Make GPIO peripheral another listable one 2017-06-08 16:25:20 -07:00
Wesley W. Terpstra
0ca609d324 vc707axi: track rocketchip API changes (#16) 2017-06-02 15:56:18 -07:00
Wesley W. Terpstra
0f8722f80c uart: power-on with the right divider for the design (#15) 2017-05-13 23:38:20 -07:00
Wesley W. Terpstra
9c8fe44670 Merge pull request #14 from sifive/async-pcie 
Async PCIe
 2017-05-12 23:15:14 -07:00
Wesley W. Terpstra
c4c158963c vc707mig: use an external ibuf 
This makes it possible to also drive a PLL of our own from the crystal.
 2017-05-12 23:07:10 -07:00
Wesley W. Terpstra
0ed21ba465 xilinxvc707pciex1: push to a dedicated clock domain 2017-05-12 23:02:44 -07:00
Wesley W. Terpstra
b3f9607512 xilinx mig: put a buffer infront of the controller (#13) 
This makes placement of the L2 and DDR controller easier.
 2017-05-11 11:50:07 -07:00
Wesley W. Terpstra
178ac84b59 xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12) 2017-05-08 01:08:37 -07:00
Henry Cook
9cb80ac913 Merge pull request #10 from sifive/axi-mmio 
axi4: switch to new pipelined converters
 2017-05-03 11:46:30 -07:00
Yunsup Lee
fd89474621 Merge pull request #11 from sifive/spi 
SPI errata fixes
 2017-05-02 14:36:39 -07:00
Albert Ou
75d6a7c6ea spi: Fix off-by-one error in calculating cycles per data frame 
Issue: Configuring the frame length to certain values causes incorrect
operation.

Symptoms: Certain frame lengths result in the master sending one extra
clock pulse.  The slave device may then become desynchronized.

Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
	* Serial mode: 0, 2, 4, 6, 8
	* Dual mode:   0, 1, 3, 5, 7, 8
	* Quad mode:   0, 1, 2, 3, 5, 6, 7, 8
 2017-05-02 12:35:34 -07:00
Albert Ou
eea10f5129 spi: Fix io.port.dq(3) output enable 
Issue: The output enable signal for DQ[3] is not driven properly.

Symptoms: Output data from master to slave is not properly transmitted
in quad mode.  Data received from the slave is unaffected.

Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol.  Do not use the Native Quad SPI protocol.
 2017-05-02 12:07:37 -07:00
Wesley W. Terpstra
a24fa9b444 axi4: switch to new pipelined converters 2017-04-26 13:10:50 -07:00
Henry Styles
6eddf517a3 Merge pull request #9 from sifive/vc707_mig_analog_inout 
Use _chisel3 analog for MIG inout
 2017-04-25 10:18:46 -07:00
Henry Styles
b882d6da93 Use _chisel3 analog for MIG inout 2017-04-25 10:15:00 -07:00
solomatnikov
b1dfcfc0b0 Added stall for read after write (#8) 2017-04-25 09:14:00 -07:00
Megan Wachs
ebd3ffa57e Merge pull request #7 from sifive/ndreset 
MockAON: Accept the non-debug interrupt as an input to overall reset.
 2017-04-10 14:25:08 -07:00
Megan Wachs
9ba47b76c6 MockAON: Accept the non-debug interrupt as an input to overall reset. 2017-04-07 16:42:32 -07:00
Megan Wachs
dbd16e305d Merge pull request #6 from sifive/debug_v013 
Debug v013
 2017-03-31 15:14:35 -07:00
Megan Wachs
70ac4044d1 spi: correct polarity of FIRRTL combo loop detection workaround. 2017-03-31 13:49:34 -07:00
Megan Wachs
1af6ce1c85 Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD 2017-03-30 20:01:30 -07:00
Jack Koenig
6a3b5e1a31 "Fix" false combinational loop through SPIArbiter 
Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
 2017-03-30 19:12:15 -07:00