Wesley W. Terpstra 0f8722f80c uart: power-on with the right divider for the design (#15)

2017-05-13 23:38:20 -07:00

src/main/scala

uart: power-on with the right divider for the design (#15)

2017-05-13 23:38:20 -07:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

Languages

Scala 99.8%

Verilog 0.2%