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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
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Scala 99.8%
Verilog 0.2%
5e51e1e931
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Yunsup Lee 5e51e1e931 uart: use PeripheryBusParams.frequency to calculate default divisor (#28)
2017-07-25 00:56:22 -07:00
src/main/scala uart: use PeripheryBusParams.frequency to calculate default divisor (#28) 2017-07-25 00:56:22 -07:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00