This website requires JavaScript.
Explore
Help
Sign In
riscv
/
sifive-blocks
Watch
1
Star
0
Fork
0
You've already forked sifive-blocks
Code
Releases
Activity
79
Commits
1
Branch
0
Tags
5e51e1e93172b5c5b6c436196f8dad68678eb93d
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Yunsup Lee
5e51e1e931
uart: use PeripheryBusParams.frequency to calculate default divisor (
#28
)
2017-07-25 00:56:22 -07:00
src/main
/scala
uart: use PeripheryBusParams.frequency to calculate default divisor (
#28
)
2017-07-25 00:56:22 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%
