commit
fd89474621
@ -41,7 +41,7 @@ class SPIFIFO(c: SPIParamsBase) extends Module {
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val proto = SPIProtocol.decode(io.link.fmt.proto).zipWithIndex
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val cnt_quot = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len >> i) })
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val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len(i, 0).orR) })
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val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (if (i > 0) io.ctrl.fmt.len(i-1, 0).orR else UInt(0)) })
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io.link.fmt <> io.ctrl.fmt
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io.link.cnt := cnt_quot + cnt_rmdr
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@ -82,7 +82,7 @@ class SPIPhysical(c: SPIParamsBase) extends Module {
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}
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val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
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val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _)
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val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _).init
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val txen = txen_in :+ txen_in.last
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io.port.sck := sck
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