This website requires JavaScript.
Explore
Help
Sign In
riscv
/
sifive-blocks
Watch
1
Star
0
Fork
0
You've already forked sifive-blocks
Code
Releases
Activity
63
Commits
1
Branch
0
Tags
27b00e177c2b4cd29234e556b3b6a0260d151431
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Megan Wachs
27b00e177c
Merge pull request
#17
from sifive/peripheral_options
...
Make more peripherals "listable" to allow for 0 or more
2017-06-09 22:07:43 -07:00
src/main
/scala
peripheral_options: Actually compiles
2017-06-09 13:53:22 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%