Yunsup Lee fd89474621 Merge pull request #11 from sifive/spi ...

SPI errata fixes

2017-05-02 14:36:39 -07:00

src/main/scala

spi: Fix off-by-one error in calculating cycles per data frame

2017-05-02 12:35:34 -07:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

Languages

Scala 99.8%

Verilog 0.2%