riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity
75 Commits 1 Branch 0 Tags
886680af49a0b7e3e5acac2678d9c5a8da9b4a5f
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Wesley W. Terpstra 886680af49 mig: fix MemoryDevice to use 'reg' properly
2017-06-29 13:41:30 -07:00
src/main/scala
mig: fix MemoryDevice to use 'reg' properly
2017-06-29 13:41:30 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
Languages
Scala 99.8%
Verilog 0.2%