Wesley W. Terpstra 66b2fd11bd vc707 axi enhancements (#24) ...

1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)

2017-06-30 12:36:33 -07:00

src/main/scala

vc707 axi enhancements (#24)

2017-06-30 12:36:33 -07:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

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