riscv/sifive-blocks
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90d3931f5aa22f00c3f6472e0b48c3a9b150db08
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Wesley W. Terpstra 90d3931f5a spi: add dts ranges field for memory mapped spi (#19)
2017-06-14 17:06:55 -07:00
src/main/scala
spi: add dts ranges field for memory mapped spi (#19)
2017-06-14 17:06:55 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
Languages
Scala 99.8%
Verilog 0.2%