Wesley W. Terpstra b3f9607512 xilinx mig: put a buffer infront of the controller (#13) ...

This makes placement of the L2 and DDR controller easier.

2017-05-11 11:50:07 -07:00

src/main/scala

xilinx mig: put a buffer infront of the controller (#13)

2017-05-11 11:50:07 -07:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

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