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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
45 Commits 1 Branch 0 Tags 280 KiB
Scala 99.8%
Verilog 0.2%
b882d6da93
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Henry Styles b882d6da93 Use _chisel3 analog for MIG inout
2017-04-25 10:15:00 -07:00
src/main/scala Use _chisel3 analog for MIG inout 2017-04-25 10:15:00 -07:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00