Henry Styles 6eddf517a3 Merge pull request #9 from sifive/vc707_mig_analog_inout ...

Use _chisel3 analog for MIG inout

2017-04-25 10:18:46 -07:00

src/main/scala

Merge pull request #9 from sifive/vc707_mig_analog_inout

2017-04-25 10:18:46 -07:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

Languages

Scala 99.8%

Verilog 0.2%