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riscv
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sifive-blocks
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b06b80dccdf4e71b37866cc0e32a800a2b1a62d1
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Megan Wachs
b06b80dccd
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
2017-06-12 17:53:51 -07:00
src/main
/scala
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
2017-06-12 17:53:51 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
S
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%
