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riscv/sifive-blocks
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d4bb8a77ea7a0a9545dcaf93a4a2a32671c2dd47
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Henry Cook d4bb8a77ea periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00
src/main/scala
periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
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Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
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Scala 99.8%
Verilog 0.2%
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