Henry Cook dacca7e7b1 Merge pull request #18 from sifive/lazy-raw-module-imp ...

periphery: convert bundle traits

2017-06-13 15:52:11 -07:00

src/main/scala

More Peripheral-to-pins cleanups

2017-06-13 11:00:29 -07:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

Languages

Scala 99.8%

Verilog 0.2%