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riscv/sifive-blocks
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84 Commits 1 Branch 0 Tags
0a80d1987d35046858c36a4fa462410b54a126f0
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Megan Wachs 0a80d1987d Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
2017-07-24 10:11:52 -07:00
src/main/scala
Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
2017-07-24 10:11:52 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
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Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
0 Stars 1 Watchers 0 Forks
Languages
Scala 99.8%
Verilog 0.2%
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