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riscv
/
sifive-blocks
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b1dfcfc0b0c303ac40c55be208e01e9dca16665e
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solomatnikov
and
GitHub
b1dfcfc0b0
Added stall for read after write (
#8
)
2017-04-25 09:14:00 -07:00
src/main
/scala
Added stall for read after write (
#8
)
2017-04-25 09:14:00 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
S
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%