Megan WachsandGitHub ebd3ffa57e Merge pull request #7 from sifive/ndreset ...

MockAON: Accept the non-debug interrupt as an input to overall reset.

2017-04-10 14:25:08 -07:00

src/main/scala

MockAON: Accept the non-debug interrupt as an input to overall reset.

2017-04-07 16:42:32 -07:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

S

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

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Verilog 0.2%