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riscv/sifive-blocks
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Megan Wachs ef4f2ed888 Remove pluralization on interface names. Require clocks and resets explicitly when necessary
2017-07-19 14:51:50 -07:00
src/main/scala
Remove pluralization on interface names. Require clocks and resets explicitly when necessary
2017-07-19 14:51:50 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
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Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
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Scala 99.8%
Verilog 0.2%
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