riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
56 Commits 1 Branch 0 Tags 280 KiB
Scala 99.8%
Verilog 0.2%
c4c158963c
Go to file
Wesley W. Terpstra c4c158963c vc707mig: use an external ibuf 
This makes it possible to also drive a PLL of our own from the crystal.
2017-05-12 23:07:10 -07:00
src/main/scala vc707mig: use an external ibuf 2017-05-12 23:07:10 -07:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00