riscv/rocket-chip
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  • 11eacda84a generalize NastiReadDataArbiter Howard Mao 2015-10-20 18:36:19 -0700
  • 3fc630405b Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale) Henry Cook 2015-10-20 15:04:39 -0700
  • 1a1185be3f Vectorize ROCC and Tile memory interfaces Henry Cook 2015-10-20 15:02:24 -0700
  • 4389b9edb0 tilelink parameter tweak: addrBits now a constant Henry Cook 2015-10-20 14:54:36 -0700
  • cedef98045 fix NASTI -> MemIO converter bug Yunsup Lee 2015-10-19 21:43:59 -0700
  • 4346111d2a fix remaining vsim harness typo Howard Mao 2015-10-19 20:20:14 -0700
  • 896aa892d1 bump uncore for TL -> NASTI converter fix Howard Mao 2015-10-19 15:31:59 -0700
  • d12403e7dc fix up and simplify TL -> NASTI converter logic Howard Mao 2015-10-19 13:47:13 -0700
  • 2cee8c8bec Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port Colin Schmidt 2015-10-18 13:09:17 -0700
  • 8c3370c2e3 L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale) Henry Cook 2015-10-16 19:15:47 -0700
  • 6f8997bee9 Minor refactor of StoreGen/AMOALU. Henry Cook 2015-10-16 19:12:21 -0700
  • 1441590c3b add enabled field to BTBParameters Henry Cook 2015-10-16 19:11:57 -0700
  • d391f97953 Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU. Henry Cook 2015-10-16 19:11:06 -0700
  • e1f573918d simplify TileLinkParameters with Option Henry Cook 2015-10-16 18:24:02 -0700
  • 49667aa4b0 make sure broadcast acquire tracker doesn't try to send requests back-to-back Howard Mao 2015-10-14 18:56:13 -0700
  • c4117eb9a2 make sure TL parameters change properly throughout Howard Mao 2015-10-14 17:59:49 -0700
  • 1d362d6d3a make sure correct parameters are used for TileLink constructors Howard Mao 2015-10-14 17:58:35 -0700
  • 969ecaecf8 pass parameters to BuildRoCC Henry Cook 2015-10-14 14:16:47 -0700
  • 4270fd78a5 Merge branch 'param-refactor-tl' Henry Cook 2015-10-14 12:16:22 -0700
  • 68cb54bc68 refactor tilelink params Henry Cook 2015-10-13 23:42:53 -0700
  • 7fa3eb95e3 refactor tilelink params Henry Cook 2015-10-13 23:42:28 -0700
  • 66ea39638e GlobalAddrMap Henry Cook 2015-10-06 18:19:45 -0700
  • 31be6407ec Removed all traces of params Henry Cook 2015-10-05 21:41:46 -0700
  • 908922c1a4 refactor NASTI to not use param Henry Cook 2015-10-02 14:20:31 -0700
  • da5fe84f53 Merge branch 'param-refactor' Henry Cook 2015-10-14 00:14:13 -0700
  • dd5052888d refactor tilelink params, compiles but ExampleSmallConfig fails Henry Cook 2015-10-13 23:44:05 -0700
  • 47da284e56 TileLinkNarrower should do nothing if interfaces are the same width Howard Mao 2015-10-13 13:28:47 -0700
  • a44e054c77 add support for different TileLink and MIF data widths Howard Mao 2015-10-13 12:46:23 -0700
  • 83df05cb6a add TileLink data narrower Howard Mao 2015-10-13 12:45:39 -0700
  • 2fee3fd0fd make sure NASTI -> SMI converter still works if words per beat is 1 Howard Mao 2015-10-13 12:44:48 -0700
  • 993ed86198 move ReorderQueue to utils.scala Howard Mao 2015-10-13 09:49:22 -0700
  • 9d11b64c75 added HasAddrMapParameters and GlobalAddrMap Henry Cook 2015-10-06 18:24:08 -0700
  • 4508666d96 log2ceil Henry Cook 2015-10-06 18:22:23 -0700
  • 8173695800 added HasAddrMapParameters Henry Cook 2015-10-06 18:20:19 -0700
  • 166df221ad added HasAddrMapParameters Henry Cook 2015-10-06 18:14:51 -0700
  • 1c489d75c1 inject params at top-level for MemDessert Henry Cook 2015-10-06 16:26:58 -0700
  • c4eadbda57 Removed all traces of params Henry Cook 2015-10-06 10:47:38 -0700
  • 38ae2707a3 refactor MemIO to not use params Henry Cook 2015-10-02 15:38:14 -0700
  • 3d10a89907 refactor NASTI to not use param; new AddrMap class Henry Cook 2015-10-02 14:23:42 -0700
  • 84576650b5 Removed all traces of params Henry Cook 2015-10-05 21:48:05 -0700
  • adcd77db36 Removed all traces of params Henry Cook 2015-10-05 20:33:55 -0700
  • 970445a26a refactor MemIO to not use params Henry Cook 2015-10-02 15:37:41 -0700
  • 69a4dd0a79 refactor NASTI to not use param Henry Cook 2015-10-02 14:20:47 -0700
  • 39a749843c refactor NASTI to not use param; new AddrMap class Henry Cook 2015-10-02 14:19:51 -0700
  • c2ad0b7dd4 Unfuck fpga-zynq submodule pointer Andrew Waterman 2015-10-01 15:00:35 -0700
  • 996670a4a6 Point to correct Chisel commit Andrew Waterman 2015-10-01 10:31:29 -0700
  • a76f0bf8fb fix involuntary release bug in rocket ProbeUnit Howard Mao 2015-09-30 17:26:48 -0700
  • 19656e4abe make sure to generate release from clean coh state on probe miss Howard Mao 2015-09-30 16:58:10 -0700
  • 8da7be3211 More Chisel3 compatibility fixes Andrew Waterman 2015-09-30 14:37:40 -0700
  • 0fe16ac1c0 Chisel3 compatibility fixes Andrew Waterman 2015-09-30 14:36:49 -0700
  • 833909a2b5 Chisel3 compatibility fixes Andrew Waterman 2015-09-30 14:36:26 -0700
  • a7c908cb83 Don't declare Reg inside of when Andrew Waterman 2015-09-30 12:43:00 -0700
  • 2f3d15675c fix DataArray writemask in L1D Howard Mao 2015-09-28 16:02:29 -0700
  • 1e7f656527 get release block address from inner release Howard Mao 2015-09-28 15:02:51 -0700
  • 79cdf6efc0 Make perf counters optional Andrew Waterman 2015-09-28 13:55:55 -0700
  • f8a7a80644 Make perf counters optional Andrew Waterman 2015-09-28 13:55:23 -0700
  • 5e88ead984 Add pseudo-ops to instructions.scala Andrew Waterman 2015-09-28 11:52:27 -0700
  • b93a94597c Remove needless control logic Andrew Waterman 2015-09-27 13:31:52 -0700
  • 353b00c8a1 revert some Chisel3-related changes and fix tlb bugs Howard Mao 2015-09-26 22:08:06 -0700
  • 4bda6b6757 fix bug in tlb refill Howard Mao 2015-09-26 21:27:36 -0700
  • 6bf8f41cef make sure passthrough requests are treated as vm_enabled = false Howard Mao 2015-09-26 20:29:51 -0700
  • c517d9f6e3 fix htif emulator constructor in vcs_main Howard Mao 2015-09-25 17:21:09 -0700
  • c3fff12ff0 Revert "replace remaining uses of Vec.fill" Andrew Waterman 2015-09-25 17:02:51 -0700
  • 3b1da4c57e Revert "replace remaining uses of Vec.fill" Andrew Waterman 2015-09-25 17:06:06 -0700
  • 20b7a82ab6 Use Vec.fill, not Vec.apply, when making Vec literals Andrew Waterman 2015-09-25 17:06:24 -0700
  • a08872c0e9 val -> def in static object Andrew Waterman 2015-09-25 17:05:28 -0700
  • e75674c0cb Revert "replace remaining uses of Vec.fill" Andrew Waterman 2015-09-25 17:05:07 -0700
  • 2179cb64ae Let isRead be true for store-conditional Andrew Waterman 2015-09-25 15:27:20 -0700
  • 0bfb2962a6 Assume coh.isRead returns true for store-conditional Andrew Waterman 2015-09-25 15:26:11 -0700
  • 7b0167b92e make sure SCR and PCR data width matches xLen Howard Mao 2015-09-25 12:13:22 -0700
  • 0e67d824b4 fix NASTI interconnect bug Howard Mao 2015-09-25 12:12:34 -0700
  • 308022210a use updated NASTI channel constructors Howard Mao 2015-09-25 12:07:27 -0700
  • 8c4ac0f4f3 make sure CSR/SCR data width matches xLen Howard Mao 2015-09-25 12:07:03 -0700
  • a9c6cced2d fix bug in NASTIArbiter Howard Mao 2015-09-25 11:03:24 -0700
  • 2e63fb291a put sensible defaults for NASTI channel constructors Howard Mao 2015-09-25 10:05:38 -0700
  • 0d763524ef make sure conf address map scales with number of cores Howard Mao 2015-09-25 09:41:19 -0700
  • 5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase Howard Mao 2015-09-25 09:02:35 -0700
  • f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE Schuyler Eldridge 2015-09-24 23:56:41 -0400
  • c20ed350a0 even more Chisel3 compatability changes Howard Mao 2015-09-24 17:55:41 -0700
  • a66bdb1956 replace remaining uses of Vec.fill Howard Mao 2015-09-24 17:53:26 -0700
  • 88b15dba60 replace remaining uses of Vec.fill Howard Mao 2015-09-24 17:51:38 -0700
  • d1f2d40a90 replace remaining uses of Vec.fill Howard Mao 2015-09-24 17:50:09 -0700
  • 3ff830e118 ReorderQueue uses Vec of Bools instead of Bits for roq_free Howard Mao 2015-09-24 17:43:53 -0700
  • 1c0111cc70 uncore merge commit Howard Mao 2015-09-24 17:10:45 -0700
  • 83740dfaa5 Merge branch 'master' of github.com:ucb-bar/uncore Howard Mao 2015-09-24 17:10:09 -0700
  • 8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO Howard Mao 2015-09-24 16:59:13 -0700
  • 4a85c5a510 pull in hardfloat fixes Howard Mao 2015-09-24 16:58:49 -0700
  • 3b86790c3f replace NASTIMasterIO and NASTISlaveIO with NASTIIO Howard Mao 2015-09-24 16:58:20 -0700
  • e3d2207c72 Chisel3 compat: merge NASTIMasterIO and NASTISlaveIO so we do not depend on flip() modifying the object Howard Mao 2015-09-24 16:57:50 -0700
  • ee6754daca Fix clone -> cloneType ducky 2015-09-24 16:16:08 -0700
  • fbc6e695d3 remove bugs from float_fix Scott Beamer 2015-09-23 16:11:47 -0700
  • 56daea793a allow float_fix to take stdin (for piping) Scott Beamer 2015-09-17 23:17:19 -0700
  • 38a9b23ce7 add a flag to only log and dump after a certain number of cycles Howard Mao 2015-09-18 18:02:03 -0700
  • 4496e8d4e2 make sure htif_emulator properly sets memory size Howard Mao 2015-09-15 10:29:45 -0700
  • 56ecdff52d Implement NASTI-based Mem/IO interconnect Howard Mao 2015-08-06 12:51:18 -0700
  • ee65f6a84d get rid of Vec.fill in IOs Howard Mao 2015-09-22 10:30:09 -0700
  • 9eb988a4c6 make sure access to invalid physical address treated as exception Howard Mao 2015-09-22 09:42:27 -0700
  • 16c748576a don't mux data_word_bypass between IOMSHR and cache Howard Mao 2015-09-10 17:57:03 -0700
  • d89bcd3922 modify csr file to bring in line with HTIF changes Howard Mao 2015-08-12 21:22:54 -0700
  • 382faba4a6 Implement bypassing L1 data cache for MMIO Howard Mao 2015-08-05 11:01:01 -0700