riscv/rocket-chip
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added HasAddrMapParameters

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This commit is contained in:
Henry Cook 2015-10-06 18:14:51 -07:00
parent adcd77db36
commit 166df221ad
3 changed files with 29 additions and 13 deletions
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27
junctions/src/main/scala/addrmap.scala
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@ -5,6 +5,33 @@ package junctions
import Chisel._
import scala.collection.mutable.HashMap
case object PAddrBits extends Field[Int]
case object VAddrBits extends Field[Int]
case object PgIdxBits extends Field[Int]
case object PgLevels extends Field[Int]
case object PgLevelBits extends Field[Int]
case object ASIdBits extends Field[Int]
case object PPNBits extends Field[Int]
case object VPNBits extends Field[Int]
case object GlobalAddrMap extends Field[AddrMap]
case object MMIOBase extends Field[BigInt]
trait HasAddrMapParameters {
implicit val p: Parameters
val paddrBits = p(PAddrBits)
val vaddrBits = p(VAddrBits)
val pgIdxBits = p(PgIdxBits)
val ppnBits = p(PPNBits)
val vpnBits = p(VPNBits)
val pgLevels = p(PgLevels)
val pgLevelBits = p(PgLevelBits)
val asIdBits = p(ASIdBits)
val addrMap = new AddrHashMap(p(GlobalAddrMap))
}
abstract class MemRegion { def size: BigInt }
case class MemSize(size: BigInt, prot: Int) extends MemRegion

9
junctions/src/main/scala/memserdes.scala
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@ -4,15 +4,6 @@ package junctions
import Chisel._
import scala.math._
case object PAddrBits extends Field[Int]
case object VAddrBits extends Field[Int]
case object PgIdxBits extends Field[Int]
case object PgLevels extends Field[Int]
case object PgLevelBits extends Field[Int]
case object ASIdBits extends Field[Int]
case object PPNBits extends Field[Int]
case object VPNBits extends Field[Int]
case object MIFAddrBits extends Field[Int]
case object MIFDataBits extends Field[Int]
case object MIFTagBits extends Field[Int]

6
junctions/src/main/scala/nasti.scala
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@ -6,8 +6,6 @@ import scala.math.max
import scala.collection.mutable.ArraySeq
case object NastiKey extends Field[NastiParameters]
case object NastiAddrMap extends Field[AddrMap]
case object MMIOBase extends Field[BigInt]
case class NastiParameters(dataBits: Int, addrBits: Int, idBits: Int)
@ -571,9 +569,9 @@ class NastiRecursiveInterconnect(
}
}
class NastiTopInterconnect(val nMasters: Int, val nSlaves: Int)
class NastiTopInterconnect(val nMasters: Int, val nSlaves: Int, addrMap: AddrMap)
(implicit p: Parameters) extends NastiInterconnect {
val temp = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, p(NastiAddrMap)))
val temp = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, addrMap))
temp.io.masters.zip(io.masters).foreach { case (t, i) =>
t.ar <> i.ar