riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Removed all traces of params

Browse Source
This commit is contained in:
Henry Cook 2015-10-06 10:47:38 -07:00
parent 38ae2707a3
commit c4eadbda57
9 changed files with 114 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
junctions

@ -1 +1 @@
Subproject commit 372e80574bc42d8b623f69b2d5bd995aa5d0a759
Subproject commit 790f01f9e5df6d9d3ecaf636ccb95d1eb751879d

2
rocket

@ -1 +1 @@
Subproject commit 21285ad7a2e6697613b03eed97f18f83d2ec317a
Subproject commit dcc32b8e6eb3b62962db952bba2e34c36137523e

48
src/main/scala/Configs.scala
View File

@ -20,19 +20,17 @@ class DefaultConfig extends ChiselConfig (
val csrs = (0 until site(NTiles)).map{ i =>
AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW))
}
val scrSize = site(HTIFNSCR) * (site(XLen) / 8)
val scrSize = site(HtifKey).nSCR * (site(XLen) / 8)
val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW))
new AddrMap(csrs :+ scr)
}
pname match {
//
case UseZscale => false
//HTIF Parameters
case HTIFWidth => Dump("HTIF_WIDTH", 16)
case HTIFNSCR => 64
case HTIFSCRDataBits => site(XLen)
case HTIFOffsetBits => site(CacheBlockOffsetBits)
case HTIFNCores => site(NTiles)
case HtifKey => HtifParameters(
width = Dump("HTIF_WIDTH", 16),
nSCR = 64,
offsetBits = site(CacheBlockOffsetBits),
nCores = site(NTiles))
//Memory Parameters
case PAddrBits => 32
case PgIdxBits => 12
@ -49,10 +47,10 @@ class DefaultConfig extends ChiselConfig (
case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
case NastiBitWidths => NastiParameters(
dataBits = site(MIFDataBits),
addrBits = site(PAddrBits),
idBits = site(MIFTagBits))
case NastiKey => NastiParameters(
dataBits = site(MIFDataBits),
addrBits = site(PAddrBits),
idBits = site(MIFTagBits))
//Params used by all caches
case NSets => findBy(CacheName)
case NWays => findBy(CacheName)
@ -74,8 +72,7 @@ class DefaultConfig extends ChiselConfig (
case Replacer => () => new RandomReplacement(site(NWays))
case AmoAluOperandBits => site(XLen)
//L1InstCache
case NBTBEntries => 62
case NRAS => 2
case BtbKey => BtbParameters()
//L1DataCache
case WordBits => site(XLen)
case StoreDataQueueDepth => 17
@ -87,14 +84,18 @@ class DefaultConfig extends ChiselConfig (
case NAcquireTransactors => 7
case L2StoreDataQueueDepth => 1
case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients))
case BuildL2CoherenceManager => () =>
Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" })
case BuildL2CoherenceManager => (p: Parameters) =>
Module(new L2BroadcastHub()(p.alterPartial({
case InnerTLId => "L1ToL2"
case OuterTLId => "L2ToMC" })))
//Tile Constants
case BuildTiles => {
TestGeneration.addSuites(rv64i.map(_("p")))
TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) }
List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1ToL2"})))
}
}
case BuildRoCC => None
case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
@ -108,12 +109,11 @@ class DefaultConfig extends ChiselConfig (
case FastLoadByte => false
case FastMulDiv => true
case XLen => 64
case NMultXpr => 32
case BuildFPU => {
val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
else TestGeneration.addSuites(env.map(rv64ufNoDiv))
Some(() => Module(new FPU))
Some((p: Parameters) => Module(new FPU()(p)))
}
case FDivSqrt => true
case SFMALatency => 2
@ -209,11 +209,11 @@ class WithL2Cache extends ChiselConfig(
case NAcquireTransactors => 2
case NSecondaryMisses => 4
case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients))
case BuildL2CoherenceManager => () =>
Module(new L2HellaCacheBank, {
case BuildL2CoherenceManager => (p: Parameters) =>
Module(new L2HellaCacheBank()(p.alterPartial({
case CacheName => "L2Bank"
case InnerTLId => "L1ToL2"
case OuterTLId => "L2ToMC"})
case OuterTLId => "L2ToMC"})))
},
knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
)
@ -235,7 +235,7 @@ class WithZscale extends ChiselConfig(
case BuildZscale => {
TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
TestGeneration.addSuites(List(zscaleBmarks))
(r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1ToL2"})))
}
case UseZscale => true
case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
@ -259,7 +259,7 @@ class SmallConfig extends ChiselConfig (
case BuildFPU => None
case FastMulDiv => false
case NTLBEntries => 4
case NBTBEntries => 8
case BtbKey => BtbParameters(nEntries = 8)
}},
knobValues = {
case "L1D_SETS" => 64

57
src/main/scala/Network.scala
View File

@ -26,12 +26,13 @@ import uncore._
* each channel on the manager side of the network
*/
abstract class RocketChipNetwork(
addrToManagerId: UInt => UInt,
sharerToClientId: UInt => UInt,
clientDepths: TileLinkDepths,
managerDepths: TileLinkDepths) extends TLModule {
val nClients = params(TLNClients)
val nManagers = params(TLNManagers)
addrToManagerId: UInt => UInt,
sharerToClientId: UInt => UInt,
clientDepths: TileLinkDepths,
managerDepths: TileLinkDepths)
(implicit p: Parameters) extends TLModule()(p) {
val nClients = p(TLNClients)
val nManagers = p(TLNManagers)
val io = new Bundle {
val clients = Vec(new ClientTileLinkIO, nClients).flip
val managers = Vec(new ManagerTileLinkIO, nManagers).flip
@ -39,21 +40,21 @@ abstract class RocketChipNetwork(
val clients = io.clients.zipWithIndex.map {
case (c, i) => {
val p = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
val q = Module(new TileLinkEnqueuer(clientDepths))
p.io.client <> c
q.io.client <> p.io.network
q.io.manager
val port = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
val qs = Module(new TileLinkEnqueuer(clientDepths))
port.io.client <> c
qs.io.client <> port.io.network
qs.io.manager
}
}
val managers = io.managers.zipWithIndex.map {
case (m, i) => {
val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
val q = Module(new TileLinkEnqueuer(managerDepths))
p.io.manager <> m
p.io.network <> q.io.manager
q.io.client
val port = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
val qs = Module(new TileLinkEnqueuer(managerDepths))
port.io.manager <> m
port.io.network <> qs.io.manager
qs.io.client
}
}
}
@ -61,10 +62,11 @@ abstract class RocketChipNetwork(
/** A simple arbiter for each channel that also deals with header-based routing.
* Assumes a single manager agent. */
class RocketChipTileLinkArbiter(
sharerToClientId: UInt => UInt = (u: UInt) => u,
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)
sharerToClientId: UInt => UInt = (u: UInt) => u,
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
(implicit p: Parameters)
extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)(p)
with TileLinkArbiterLike
with PassesId {
val arbN = nClients
@ -86,13 +88,14 @@ class RocketChipTileLinkArbiter(
* port id are done automatically.
*/
class RocketChipTileLinkCrossbar(
addrToManagerId: UInt => UInt = u => UInt(0),
sharerToClientId: UInt => UInt = u => u,
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths) {
val n = params(LNEndpoints)
val count = params(TLDataBeats)
addrToManagerId: UInt => UInt = u => UInt(0),
sharerToClientId: UInt => UInt = u => u,
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
(implicit p: Parameters)
extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
val n = p(LNEndpoints)
val count = p(TLDataBeats)
// Actually instantiate the particular networks required for TileLink
val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))

72
src/main/scala/RocketChip.scala
View File

@ -23,17 +23,17 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
/** Whether to use the slow backup memory port [VLSI] */
case object UseBackupMemoryPort extends Field[Boolean]
/** Function for building some kind of coherence manager agent */
case object BuildL2CoherenceManager extends Field[() => CoherenceAgent]
case object BuildL2CoherenceManager extends Field[Parameters => CoherenceAgent]
/** Function for building some kind of tile connected to a reset signal */
case object BuildTiles extends Field[Seq[(Bool) => Tile]]
case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
/** Start address of the "io" region in the memory map */
case object ExternalIOStart extends Field[BigInt]
/** Utility trait for quick access to some relevant parameters */
trait TopLevelParameters extends UsesParameters {
implicit val p: Parameters
lazy val htifW = p(HTIFWidth)
trait HasTopLevelParameters extends HasHtifParameters {
lazy val nTiles = p(NTiles)
lazy val htifW = w
lazy val csrAddrBits = 12
lazy val nMemChannels = p(NMemoryChannels)
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
lazy val nBanks = nMemChannels*nBanksPerMemChannel
@ -41,8 +41,6 @@ trait TopLevelParameters extends UsesParameters {
lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
lazy val mifAddrBits = p(MIFAddrBits)
lazy val mifDataBeats = p(MIFDataBeats)
lazy val scrAddrBits = log2Up(p(HTIFNSCR))
lazy val pcrAddrBits = 12
lazy val xLen = p(XLen)
//require(lsb + log2Up(nBanks) < mifAddrBits)
}
@ -55,23 +53,24 @@ class MemBackupCtrlIO extends Bundle {
}
/** Top-level io for the chip */
class BasicTopIO extends Bundle {
class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasTopLevelParameters {
val host = new HostIO
val mem_backup_ctrl = new MemBackupCtrlIO
}
class TopIO(implicit val p: Parameters) extends BasicTopIO {
class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem = new MemIO
}
class MultiChannelTopIO(implicit val p: Parameters) extends BasicTopIO with TopLevelParameters {
class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem = Vec(new NastiIO, nMemChannels)
val mmio = new NastiIO
}
/** Top-level module for the chip */
//TODO: Remove this wrapper once multichannel DRAM controller is provided
class Top extends Module with TopLevelParameters {
class Top extends Module with HasTopLevelParameters {
implicit val p = params
val io = new TopIO
if(!p(UseZscale)) {
@ -95,24 +94,24 @@ class Top extends Module with TopLevelParameters {
}
}
class MultiChannelTop(implicit val p: Parameters) extends Module with TopLevelParameters {
class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
val io = new MultiChannelTopIO
// Build an Uncore and a set of Tiles
val innerTLParams = p.alterPartial({case TLId => "L1ToL2" })
val uncore = Module(new Uncore()(innerTLParams))(innerTLParams)
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset) }
val uncore = Module(new Uncore()(innerTLParams))
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
// Connect each tile to the HTIF
uncore.io.htif.zip(tileList).zipWithIndex.foreach {
case ((hl, tile), i) =>
tile.io.host.id := UInt(i)
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.pcr.req <> Queue(hl.pcr.req)
hl.pcr.resp <> Queue(tile.io.host.pcr.resp)
tile.io.host.csr.req <> Queue(hl.csr.req)
hl.csr.resp <> Queue(tile.io.host.csr.resp)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
hl.debug_stats_csr := tile.io.host.debug_stats_csr
}
// Connect the uncore to the tile memory ports, HostIO and MemIO
@ -129,18 +128,18 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with TopLevelPa
* Usually this is clocked and/or place-and-routed separately from the Tiles.
* Contains the Host-Target InterFace module (HTIF).
*/
class Uncore(implicit val p: Parameters) extends Module with TopLevelParameters {
class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
val io = new Bundle {
val host = new HostIO
val mem = Vec(new NastiIO, nMemChannels)
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val htif = Vec(new HTIFIO, nTiles).flip
val htif = Vec(new HtifIO, nTiles).flip
val mem_backup_ctrl = new MemBackupCtrlIO
val mmio = new NastiIO
}
val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
outmemsys.io.incoherent := htif.io.cpu.map(_.reset)
outmemsys.io.htif_uncached <> htif.io.mem
@ -152,25 +151,24 @@ class Uncore(implicit val p: Parameters) extends Module with TopLevelParameters
io.htif(i).id := htif.io.cpu(i).id
htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
htif.io.cpu(i).debug_stats_pcr <> io.htif(i).debug_stats_pcr
htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
val pcr_arb = Module(new SMIArbiter(2, 64, 12))
pcr_arb.io.in(0) <> htif.io.cpu(i).pcr
pcr_arb.io.in(1) <> outmemsys.io.pcr(i)
io.htif(i).pcr <> pcr_arb.io.out
val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))
csr_arb.io.in(0) <> htif.io.cpu(i).csr
csr_arb.io.in(1) <> outmemsys.io.csr(i)
io.htif(i).csr <> csr_arb.io.out
}
// Arbitrate SCR access between MMIO and HTIF
val scrArb = Module(new SMIArbiter(2, 64, scrAddrBits))
val scrFile = Module(new SCRFile)
val scrArb = Module(new SMIArbiter(2, scrDataBits, scrAddrBits))
scrArb.io.in(0) <> htif.io.scr
scrArb.io.in(1) <> outmemsys.io.scr
scrFile.io.smi <> scrArb.io.out
// scrFile.io.scr <> (... your SCR connections ...)
// Wire the htif to the memory port(s) and host interface
io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
io.host.debug_stats_csr := htif.io.host.debug_stats_csr
io.mem <> outmemsys.io.mem
io.mmio <> outmemsys.io.mmio
if(p(UseBackupMemoryPort)) {
@ -186,7 +184,7 @@ class Uncore(implicit val p: Parameters) extends Module with TopLevelParameters
/** The whole outer memory hierarchy, including a NoC, some kind of coherence
* manager agent, and a converter from TileLink to MemIO.
*/
class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevelParameters {
class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters {
val io = new Bundle {
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
@ -195,7 +193,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
val mem = Vec(new NastiIO, nMemChannels)
val mem_backup = new MemSerializedIO(htifW)
val mem_backup_en = Bool(INPUT)
val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles)
val csr = Vec(new SMIIO(xLen, csrAddrBits), nTiles)
val scr = new SMIIO(xLen, scrAddrBits)
val mmio = new NastiIO
}
@ -214,7 +212,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
// Create point(s) of coherence serialization
val nManagers = nMemChannels * nBanksPerMemChannel
val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)()}
val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)(p)}
managerEndpoints.foreach { _.incoherent := io.incoherent }
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
@ -238,8 +236,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves)(p))
for ((bank, i) <- managerEndpoints.zipWithIndex) {
val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
val conv = Module(new NastiIOTileLinkIOConverter)(outerTLParams)
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
val conv = Module(new NastiIOTileLinkIOConverter()(outerTLParams))
unwrap.io.in <> bank.outerTL
conv.io.tl <> unwrap.io.out
interconnect.io.masters(i) <> conv.io.nasti
@ -251,12 +249,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i"
val csrPort = addrMap(csrName).port
val conv = Module(new SMIIONastiIOConverter(xLen, pcrAddrBits))
val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
conv.io.nasti <> interconnect.io.slaves(csrPort)
io.pcr(i) <> conv.io.smi
io.csr(i) <> conv.io.smi
}
val conv = Module(new SMIIONastiIOConverter(xLen, scrAddrBits))
val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
io.scr <> conv.io.smi
@ -268,6 +266,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
if(p(UseBackupMemoryPort)) {
VLSIUtils.doOuterMemorySystemSerdes(
mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
nMemChannels, p(HTIFWidth), p(CacheBlockOffsetBits))
nMemChannels, htifW, p(CacheBlockOffsetBits))
} else { io.mem <> mem_channels }
}

4
src/main/scala/Vlsi.scala
View File

@ -7,8 +7,8 @@ import junctions._
import uncore._
class MemDessert(implicit val p: Parameters) extends Module {
val io = new MemDesserIO(p(HTIFWidth))
val x = Module(new MemDesser(p(HTIFWidth)))
val io = new MemDesserIO(p(HtifKey).width)
val x = Module(new MemDesser(p(HtifKey).width))
io.narrow <> x.io.narrow
io.wide <> x.io.wide
}

38
src/main/scala/ZscaleChip.scala
View File

@ -9,22 +9,22 @@ import rocket._
import zscale._
case object UseZscale extends Field[Boolean]
case object BuildZscale extends Field[(Bool) => Zscale]
case object BuildZscale extends Field[(Bool, Parameters) => Zscale]
case object BootROMCapacity extends Field[Int]
case object DRAMCapacity extends Field[Int]
class ZscaleSystem extends Module {
class ZscaleSystem(implicit p: Parameters) extends Module {
val io = new Bundle {
val host = new HTIFIO
val jtag = new HASTIMasterIO().flip
val bootmem = new HASTISlaveIO().flip
val dram = new HASTISlaveIO().flip
val spi = new HASTISlaveIO().flip
val led = new POCIIO
val corereset = new POCIIO
val host = new HtifIO
val jtag = new HastiMasterIO().flip
val bootmem = new HastiSlaveIO().flip
val dram = new HastiSlaveIO().flip
val spi = new HastiSlaveIO().flip
val led = new PociIO
val corereset = new PociIO
}
val core = params(BuildZscale)(io.host.reset)
val core = p(BuildZscale)(io.host.reset, p)
val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
@ -36,11 +36,11 @@ class ZscaleSystem extends Module {
val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
val xbar = Module(new HASTIXbar(3, Seq(bootmem_afn, sbus_afn)))
val sadapter = Module(new HASTISlaveToMaster)
val sbus = Module(new HASTIBus(Seq(dram_afn, spi_afn, pbus_afn)))
val padapter = Module(new HASTItoPOCIBridge)
val pbus = Module(new POCIBus(Seq(led_afn, corereset_afn)))
val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn)))
val sadapter = Module(new HastiSlaveToMaster)
val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn)))
val padapter = Module(new HastiToPociBridge)
val pbus = Module(new PociBus(Seq(led_afn, corereset_afn)))
core.io.host <> io.host
xbar.io.masters(0) <> io.jtag
@ -60,14 +60,14 @@ class ZscaleSystem extends Module {
io.corereset <> pbus.io.slaves(1)
}
class ZscaleTop extends Module {
class ZscaleTop(implicit p: Parameters) extends Module {
val io = new Bundle {
val host = new HTIFIO
val host = new HtifIO
}
val sys = Module(new ZscaleSystem)
val bootmem = Module(new HASTISRAM(params(BootROMCapacity)/4))
val dram = Module(new HASTISRAM(params(DRAMCapacity)/4))
val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4))
val dram = Module(new HastiSRAM(p(DRAMCapacity)/4))
sys.io.host <> io.host
bootmem.io <> sys.io.bootmem

2
uncore

@ -1 +1 @@
Subproject commit c533b99105a84d3969e9baccabf402fe7296711a
Subproject commit c824028e4f38006058ae0757a5339e3273e0ee2b

2
zscale

@ -1 +1 @@
Subproject commit 461e7ee16bb15144e14c42855bf2ee23abd51806
Subproject commit 3338af40491ccfe4b403761d755372c201003e39