Removed all traces of params
This commit is contained in:
Henry Cook
parent
38ae2707a3
commit
c4eadbda57
@ -1 +1 @@
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Subproject commit 372e80574bc42d8b623f69b2d5bd995aa5d0a759
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Subproject commit 790f01f9e5df6d9d3ecaf636ccb95d1eb751879d
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2
rocket
2
rocket
@ -1 +1 @@
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Subproject commit 21285ad7a2e6697613b03eed97f18f83d2ec317a
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Subproject commit dcc32b8e6eb3b62962db952bba2e34c36137523e
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@ -20,19 +20,17 @@ class DefaultConfig extends ChiselConfig (
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val csrs = (0 until site(NTiles)).map{ i =>
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AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW))
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}
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val scrSize = site(HTIFNSCR) * (site(XLen) / 8)
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val scrSize = site(HtifKey).nSCR * (site(XLen) / 8)
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val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW))
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new AddrMap(csrs :+ scr)
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}
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pname match {
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//
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case UseZscale => false
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//HTIF Parameters
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case HTIFWidth => Dump("HTIF_WIDTH", 16)
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case HTIFNSCR => 64
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case HTIFSCRDataBits => site(XLen)
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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case HtifKey => HtifParameters(
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width = Dump("HTIF_WIDTH", 16),
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nSCR = 64,
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offsetBits = site(CacheBlockOffsetBits),
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nCores = site(NTiles))
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//Memory Parameters
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case PAddrBits => 32
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case PgIdxBits => 12
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@ -49,10 +47,10 @@ class DefaultConfig extends ChiselConfig (
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
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case NastiBitWidths => NastiParameters(
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dataBits = site(MIFDataBits),
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addrBits = site(PAddrBits),
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idBits = site(MIFTagBits))
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case NastiKey => NastiParameters(
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dataBits = site(MIFDataBits),
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addrBits = site(PAddrBits),
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idBits = site(MIFTagBits))
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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@ -74,8 +72,7 @@ class DefaultConfig extends ChiselConfig (
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case Replacer => () => new RandomReplacement(site(NWays))
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case AmoAluOperandBits => site(XLen)
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//L1InstCache
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case NBTBEntries => 62
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case NRAS => 2
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case BtbKey => BtbParameters()
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//L1DataCache
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case WordBits => site(XLen)
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case StoreDataQueueDepth => 17
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@ -87,14 +84,18 @@ class DefaultConfig extends ChiselConfig (
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" })
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1ToL2"
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case OuterTLId => "L2ToMC" })))
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//Tile Constants
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case BuildTiles => {
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TestGeneration.addSuites(rv64i.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
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TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
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List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) }
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1ToL2"})))
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}
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}
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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@ -108,12 +109,11 @@ class DefaultConfig extends ChiselConfig (
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case FastLoadByte => false
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case FastMulDiv => true
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case XLen => 64
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case NMultXpr => 32
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case BuildFPU => {
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val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
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if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
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else TestGeneration.addSuites(env.map(rv64ufNoDiv))
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Some(() => Module(new FPU))
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Some((p: Parameters) => Module(new FPU()(p)))
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}
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case FDivSqrt => true
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case SFMALatency => 2
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@ -209,11 +209,11 @@ class WithL2Cache extends ChiselConfig(
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2HellaCacheBank, {
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheName => "L2Bank"
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case InnerTLId => "L1ToL2"
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case OuterTLId => "L2ToMC"})
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case OuterTLId => "L2ToMC"})))
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
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)
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@ -235,7 +235,7 @@ class WithZscale extends ChiselConfig(
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case BuildZscale => {
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TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
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TestGeneration.addSuites(List(zscaleBmarks))
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(r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
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(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1ToL2"})))
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}
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case UseZscale => true
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case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
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@ -259,7 +259,7 @@ class SmallConfig extends ChiselConfig (
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case BuildFPU => None
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case FastMulDiv => false
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case NTLBEntries => 4
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case NBTBEntries => 8
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case BtbKey => BtbParameters(nEntries = 8)
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}},
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knobValues = {
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case "L1D_SETS" => 64
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@ -26,12 +26,13 @@ import uncore._
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* each channel on the manager side of the network
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*/
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abstract class RocketChipNetwork(
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addrToManagerId: UInt => UInt,
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sharerToClientId: UInt => UInt,
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clientDepths: TileLinkDepths,
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managerDepths: TileLinkDepths) extends TLModule {
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val nClients = params(TLNClients)
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val nManagers = params(TLNManagers)
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addrToManagerId: UInt => UInt,
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sharerToClientId: UInt => UInt,
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clientDepths: TileLinkDepths,
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managerDepths: TileLinkDepths)
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(implicit p: Parameters) extends TLModule()(p) {
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val nClients = p(TLNClients)
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val nManagers = p(TLNManagers)
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val io = new Bundle {
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val clients = Vec(new ClientTileLinkIO, nClients).flip
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val managers = Vec(new ManagerTileLinkIO, nManagers).flip
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@ -39,21 +40,21 @@ abstract class RocketChipNetwork(
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val clients = io.clients.zipWithIndex.map {
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case (c, i) => {
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val p = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
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val q = Module(new TileLinkEnqueuer(clientDepths))
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p.io.client <> c
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q.io.client <> p.io.network
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q.io.manager
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val port = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
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val qs = Module(new TileLinkEnqueuer(clientDepths))
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port.io.client <> c
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qs.io.client <> port.io.network
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qs.io.manager
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}
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}
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val managers = io.managers.zipWithIndex.map {
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case (m, i) => {
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val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
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val q = Module(new TileLinkEnqueuer(managerDepths))
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p.io.manager <> m
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p.io.network <> q.io.manager
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q.io.client
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val port = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
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val qs = Module(new TileLinkEnqueuer(managerDepths))
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port.io.manager <> m
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port.io.network <> qs.io.manager
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qs.io.client
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}
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}
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}
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@ -61,10 +62,11 @@ abstract class RocketChipNetwork(
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/** A simple arbiter for each channel that also deals with header-based routing.
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* Assumes a single manager agent. */
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class RocketChipTileLinkArbiter(
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sharerToClientId: UInt => UInt = (u: UInt) => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)
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sharerToClientId: UInt => UInt = (u: UInt) => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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(implicit p: Parameters)
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extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)(p)
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with TileLinkArbiterLike
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with PassesId {
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val arbN = nClients
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@ -86,13 +88,14 @@ class RocketChipTileLinkArbiter(
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* port id are done automatically.
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*/
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class RocketChipTileLinkCrossbar(
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addrToManagerId: UInt => UInt = u => UInt(0),
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sharerToClientId: UInt => UInt = u => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths) {
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val n = params(LNEndpoints)
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val count = params(TLDataBeats)
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addrToManagerId: UInt => UInt = u => UInt(0),
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sharerToClientId: UInt => UInt = u => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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(implicit p: Parameters)
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extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
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val n = p(LNEndpoints)
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val count = p(TLDataBeats)
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// Actually instantiate the particular networks required for TileLink
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val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
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val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))
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@ -23,17 +23,17 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Whether to use the slow backup memory port [VLSI] */
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case object UseBackupMemoryPort extends Field[Boolean]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[() => CoherenceAgent]
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case object BuildL2CoherenceManager extends Field[Parameters => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool) => Tile]]
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** Start address of the "io" region in the memory map */
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case object ExternalIOStart extends Field[BigInt]
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/** Utility trait for quick access to some relevant parameters */
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trait TopLevelParameters extends UsesParameters {
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implicit val p: Parameters
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lazy val htifW = p(HTIFWidth)
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trait HasTopLevelParameters extends HasHtifParameters {
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lazy val nTiles = p(NTiles)
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lazy val htifW = w
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lazy val csrAddrBits = 12
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val nBanks = nMemChannels*nBanksPerMemChannel
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@ -41,8 +41,6 @@ trait TopLevelParameters extends UsesParameters {
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lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
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lazy val mifAddrBits = p(MIFAddrBits)
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lazy val mifDataBeats = p(MIFDataBeats)
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lazy val scrAddrBits = log2Up(p(HTIFNSCR))
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lazy val pcrAddrBits = 12
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lazy val xLen = p(XLen)
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//require(lsb + log2Up(nBanks) < mifAddrBits)
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}
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@ -55,23 +53,24 @@ class MemBackupCtrlIO extends Bundle {
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}
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/** Top-level io for the chip */
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class BasicTopIO extends Bundle {
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters {
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val host = new HostIO
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val mem_backup_ctrl = new MemBackupCtrlIO
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}
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class TopIO(implicit val p: Parameters) extends BasicTopIO {
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem = new MemIO
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}
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class MultiChannelTopIO(implicit val p: Parameters) extends BasicTopIO with TopLevelParameters {
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class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem = Vec(new NastiIO, nMemChannels)
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val mmio = new NastiIO
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}
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/** Top-level module for the chip */
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//TODO: Remove this wrapper once multichannel DRAM controller is provided
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class Top extends Module with TopLevelParameters {
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class Top extends Module with HasTopLevelParameters {
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implicit val p = params
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val io = new TopIO
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if(!p(UseZscale)) {
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@ -95,24 +94,24 @@ class Top extends Module with TopLevelParameters {
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}
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}
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class MultiChannelTop(implicit val p: Parameters) extends Module with TopLevelParameters {
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class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
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val io = new MultiChannelTopIO
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// Build an Uncore and a set of Tiles
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val innerTLParams = p.alterPartial({case TLId => "L1ToL2" })
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val uncore = Module(new Uncore()(innerTLParams))(innerTLParams)
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val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset) }
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val uncore = Module(new Uncore()(innerTLParams))
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val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
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// Connect each tile to the HTIF
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uncore.io.htif.zip(tileList).zipWithIndex.foreach {
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case ((hl, tile), i) =>
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.pcr.req <> Queue(hl.pcr.req)
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hl.pcr.resp <> Queue(tile.io.host.pcr.resp)
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tile.io.host.csr.req <> Queue(hl.csr.req)
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hl.csr.resp <> Queue(tile.io.host.csr.resp)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
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hl.debug_stats_csr := tile.io.host.debug_stats_csr
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}
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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@ -129,18 +128,18 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with TopLevelPa
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* Usually this is clocked and/or place-and-routed separately from the Tiles.
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* Contains the Host-Target InterFace module (HTIF).
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*/
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class Uncore(implicit val p: Parameters) extends Module with TopLevelParameters {
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class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
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val io = new Bundle {
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val host = new HostIO
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val mem = Vec(new NastiIO, nMemChannels)
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val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
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val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
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val htif = Vec(new HTIFIO, nTiles).flip
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val htif = Vec(new HtifIO, nTiles).flip
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val mem_backup_ctrl = new MemBackupCtrlIO
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val mmio = new NastiIO
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}
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val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
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val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
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val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
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outmemsys.io.incoherent := htif.io.cpu.map(_.reset)
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outmemsys.io.htif_uncached <> htif.io.mem
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@ -152,25 +151,24 @@ class Uncore(implicit val p: Parameters) extends Module with TopLevelParameters
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io.htif(i).id := htif.io.cpu(i).id
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htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
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io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
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htif.io.cpu(i).debug_stats_pcr <> io.htif(i).debug_stats_pcr
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htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
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val pcr_arb = Module(new SMIArbiter(2, 64, 12))
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pcr_arb.io.in(0) <> htif.io.cpu(i).pcr
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pcr_arb.io.in(1) <> outmemsys.io.pcr(i)
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io.htif(i).pcr <> pcr_arb.io.out
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val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))
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csr_arb.io.in(0) <> htif.io.cpu(i).csr
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csr_arb.io.in(1) <> outmemsys.io.csr(i)
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io.htif(i).csr <> csr_arb.io.out
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}
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// Arbitrate SCR access between MMIO and HTIF
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val scrArb = Module(new SMIArbiter(2, 64, scrAddrBits))
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val scrFile = Module(new SCRFile)
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val scrArb = Module(new SMIArbiter(2, scrDataBits, scrAddrBits))
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scrArb.io.in(0) <> htif.io.scr
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scrArb.io.in(1) <> outmemsys.io.scr
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scrFile.io.smi <> scrArb.io.out
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// scrFile.io.scr <> (... your SCR connections ...)
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// Wire the htif to the memory port(s) and host interface
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io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
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io.host.debug_stats_csr := htif.io.host.debug_stats_csr
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io.mem <> outmemsys.io.mem
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io.mmio <> outmemsys.io.mmio
|
||||
if(p(UseBackupMemoryPort)) {
|
||||
@ -186,7 +184,7 @@ class Uncore(implicit val p: Parameters) extends Module with TopLevelParameters
|
||||
/** The whole outer memory hierarchy, including a NoC, some kind of coherence
|
||||
* manager agent, and a converter from TileLink to MemIO.
|
||||
*/
|
||||
class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevelParameters {
|
||||
class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters {
|
||||
val io = new Bundle {
|
||||
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
|
||||
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
|
||||
@ -195,7 +193,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
|
||||
val mem = Vec(new NastiIO, nMemChannels)
|
||||
val mem_backup = new MemSerializedIO(htifW)
|
||||
val mem_backup_en = Bool(INPUT)
|
||||
val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles)
|
||||
val csr = Vec(new SMIIO(xLen, csrAddrBits), nTiles)
|
||||
val scr = new SMIIO(xLen, scrAddrBits)
|
||||
val mmio = new NastiIO
|
||||
}
|
||||
@ -214,7 +212,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
|
||||
|
||||
// Create point(s) of coherence serialization
|
||||
val nManagers = nMemChannels * nBanksPerMemChannel
|
||||
val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)()}
|
||||
val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)(p)}
|
||||
managerEndpoints.foreach { _.incoherent := io.incoherent }
|
||||
|
||||
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
|
||||
@ -238,8 +236,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
|
||||
val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves)(p))
|
||||
|
||||
for ((bank, i) <- managerEndpoints.zipWithIndex) {
|
||||
val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
|
||||
val conv = Module(new NastiIOTileLinkIOConverter)(outerTLParams)
|
||||
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
|
||||
val conv = Module(new NastiIOTileLinkIOConverter()(outerTLParams))
|
||||
unwrap.io.in <> bank.outerTL
|
||||
conv.io.tl <> unwrap.io.out
|
||||
interconnect.io.masters(i) <> conv.io.nasti
|
||||
@ -251,12 +249,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
|
||||
for (i <- 0 until nTiles) {
|
||||
val csrName = s"conf:csr$i"
|
||||
val csrPort = addrMap(csrName).port
|
||||
val conv = Module(new SMIIONastiIOConverter(xLen, pcrAddrBits))
|
||||
val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
|
||||
conv.io.nasti <> interconnect.io.slaves(csrPort)
|
||||
io.pcr(i) <> conv.io.smi
|
||||
io.csr(i) <> conv.io.smi
|
||||
}
|
||||
|
||||
val conv = Module(new SMIIONastiIOConverter(xLen, scrAddrBits))
|
||||
val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
|
||||
conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
|
||||
io.scr <> conv.io.smi
|
||||
|
||||
@ -268,6 +266,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevel
|
||||
if(p(UseBackupMemoryPort)) {
|
||||
VLSIUtils.doOuterMemorySystemSerdes(
|
||||
mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
|
||||
nMemChannels, p(HTIFWidth), p(CacheBlockOffsetBits))
|
||||
nMemChannels, htifW, p(CacheBlockOffsetBits))
|
||||
} else { io.mem <> mem_channels }
|
||||
}
|
||||
|
||||
@ -7,8 +7,8 @@ import junctions._
|
||||
import uncore._
|
||||
|
||||
class MemDessert(implicit val p: Parameters) extends Module {
|
||||
val io = new MemDesserIO(p(HTIFWidth))
|
||||
val x = Module(new MemDesser(p(HTIFWidth)))
|
||||
val io = new MemDesserIO(p(HtifKey).width)
|
||||
val x = Module(new MemDesser(p(HtifKey).width))
|
||||
io.narrow <> x.io.narrow
|
||||
io.wide <> x.io.wide
|
||||
}
|
||||
|
||||
@ -9,22 +9,22 @@ import rocket._
|
||||
import zscale._
|
||||
|
||||
case object UseZscale extends Field[Boolean]
|
||||
case object BuildZscale extends Field[(Bool) => Zscale]
|
||||
case object BuildZscale extends Field[(Bool, Parameters) => Zscale]
|
||||
case object BootROMCapacity extends Field[Int]
|
||||
case object DRAMCapacity extends Field[Int]
|
||||
|
||||
class ZscaleSystem extends Module {
|
||||
class ZscaleSystem(implicit p: Parameters) extends Module {
|
||||
val io = new Bundle {
|
||||
val host = new HTIFIO
|
||||
val jtag = new HASTIMasterIO().flip
|
||||
val bootmem = new HASTISlaveIO().flip
|
||||
val dram = new HASTISlaveIO().flip
|
||||
val spi = new HASTISlaveIO().flip
|
||||
val led = new POCIIO
|
||||
val corereset = new POCIIO
|
||||
val host = new HtifIO
|
||||
val jtag = new HastiMasterIO().flip
|
||||
val bootmem = new HastiSlaveIO().flip
|
||||
val dram = new HastiSlaveIO().flip
|
||||
val spi = new HastiSlaveIO().flip
|
||||
val led = new PociIO
|
||||
val corereset = new PociIO
|
||||
}
|
||||
|
||||
val core = params(BuildZscale)(io.host.reset)
|
||||
val core = p(BuildZscale)(io.host.reset, p)
|
||||
|
||||
val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
|
||||
|
||||
@ -36,11 +36,11 @@ class ZscaleSystem extends Module {
|
||||
val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
|
||||
val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
|
||||
|
||||
val xbar = Module(new HASTIXbar(3, Seq(bootmem_afn, sbus_afn)))
|
||||
val sadapter = Module(new HASTISlaveToMaster)
|
||||
val sbus = Module(new HASTIBus(Seq(dram_afn, spi_afn, pbus_afn)))
|
||||
val padapter = Module(new HASTItoPOCIBridge)
|
||||
val pbus = Module(new POCIBus(Seq(led_afn, corereset_afn)))
|
||||
val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn)))
|
||||
val sadapter = Module(new HastiSlaveToMaster)
|
||||
val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn)))
|
||||
val padapter = Module(new HastiToPociBridge)
|
||||
val pbus = Module(new PociBus(Seq(led_afn, corereset_afn)))
|
||||
|
||||
core.io.host <> io.host
|
||||
xbar.io.masters(0) <> io.jtag
|
||||
@ -60,14 +60,14 @@ class ZscaleSystem extends Module {
|
||||
io.corereset <> pbus.io.slaves(1)
|
||||
}
|
||||
|
||||
class ZscaleTop extends Module {
|
||||
class ZscaleTop(implicit p: Parameters) extends Module {
|
||||
val io = new Bundle {
|
||||
val host = new HTIFIO
|
||||
val host = new HtifIO
|
||||
}
|
||||
|
||||
val sys = Module(new ZscaleSystem)
|
||||
val bootmem = Module(new HASTISRAM(params(BootROMCapacity)/4))
|
||||
val dram = Module(new HASTISRAM(params(DRAMCapacity)/4))
|
||||
val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4))
|
||||
val dram = Module(new HastiSRAM(p(DRAMCapacity)/4))
|
||||
|
||||
sys.io.host <> io.host
|
||||
bootmem.io <> sys.io.bootmem
|
||||
|
||||
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit c533b99105a84d3969e9baccabf402fe7296711a
|
||||
Subproject commit c824028e4f38006058ae0757a5339e3273e0ee2b
|
||||
2
zscale
2
zscale
@ -1 +1 @@
|
||||
Subproject commit 461e7ee16bb15144e14c42855bf2ee23abd51806
|
||||
Subproject commit 3338af40491ccfe4b403761d755372c201003e39
|
||||
Loading…
Reference in New Issue
Block a user