get rid of Vec.fill in IOs
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@ -238,7 +238,7 @@ class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule wi
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/** Arbitrate among arbN masters requesting to a single slave */
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class NASTIArbiter(val arbN: Int) extends NASTIModule {
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val io = new Bundle {
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val master = Vec.fill(arbN) { new NASTISlaveIO }
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val master = Vec(new NASTISlaveIO, arbN)
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val slave = new NASTIMasterIO
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}
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@ -306,7 +306,7 @@ class NASTIArbiter(val arbN: Int) extends NASTIModule {
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* Arbiter locks until last message in channel is sent */
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class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
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val io = new Bundle {
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val in = Vec.fill(arbN) { Decoupled(new NASTIReadDataChannel) }.flip
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val in = Vec(Decoupled(new NASTIReadDataChannel), arbN).flip
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val out = Decoupled(new NASTIReadDataChannel)
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}
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@ -402,7 +402,7 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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val io = new Bundle {
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val master = new NASTISlaveIO
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val slave = Vec.fill(nSlaves) { new NASTIMasterIO }
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val slave = Vec(new NASTIMasterIO, nSlaves)
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}
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var ar_ready = Bool(false)
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@ -479,8 +479,8 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
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extends NASTIModule {
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val io = new Bundle {
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val masters = Vec.fill(nMasters) { new NASTISlaveIO }
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val slaves = Vec.fill(nSlaves) { new NASTIMasterIO }
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val masters = Vec(new NASTISlaveIO, nMasters)
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val slaves = Vec(new NASTIMasterIO, nSlaves)
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}
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val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io }
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@ -594,8 +594,8 @@ case object NASTIAddrHashMap extends Field[AddrHashMap]
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class NASTIInterconnectIO(val nMasters: Int, val nSlaves: Int) extends Bundle {
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/* This is a bit confusing. The interconnect is a slave to the masters and
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* a master to the slaves. Hence why the declarations seem to be backwards. */
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val masters = Vec.fill(nMasters) { new NASTISlaveIO }
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val slaves = Vec.fill(nSlaves) { new NASTIMasterIO }
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val masters = Vec(new NASTISlaveIO, nMasters)
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val slaves = Vec(new NASTIMasterIO, nSlaves)
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override def cloneType =
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new NASTIInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
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}
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@ -58,7 +58,7 @@ class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral {
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class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
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extends Module {
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val io = new Bundle {
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val in = Vec.fill(n) { new SMIIO(dataWidth, addrWidth) }.flip
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val in = Vec(new SMIIO(dataWidth, addrWidth), n).flip
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val out = new SMIIO(dataWidth, addrWidth)
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}
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