Merge branch 'param-refactor-tl'
This commit is contained in:
Henry Cook
commit
4270fd78a5
@ -1 +1 @@
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Subproject commit 70a5971a223380f9334105aa715ba38fad9ef5f2
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Subproject commit 5f099ddb2186687d3e309e870676e63c8844e7e0
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2
rocket
2
rocket
@ -1 +1 @@
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Subproject commit ca26680973158727c4c7dcbff0d3054b988d5f7a
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Subproject commit 4d29d5c48cfaa3800bf5b6d5428a9c6e83335477
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@ -15,25 +15,22 @@ class DefaultConfig extends ChiselConfig (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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def genCsrAddrMap() = {
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val xLen = site(XLen)
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val nSCR = site(HTIFNSCR)
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val csrSize = (1 << 12) * (xLen / 8)
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val nTiles = site(NTiles)
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(0 until nTiles)
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.map(i => (s"csr$i", None, MemSize(csrSize, AddrMap.RW))) :+
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("scr", None, MemSize(nSCR * xLen / 8, AddrMap.RW))
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def genCsrAddrMap: AddrMap = {
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val csrSize = (1 << 12) * (site(XLen) / 8)
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val csrs = (0 until site(NTiles)).map{ i =>
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AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW))
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}
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val scrSize = site(HtifKey).nSCR * (site(XLen) / 8)
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val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW))
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new AddrMap(csrs :+ scr)
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}
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pname match {
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//
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case UseZscale => false
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//HTIF Parameters
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case HTIFWidth => Dump("HTIF_WIDTH", 16)
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case HTIFNSCR => 64
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case HTIFSCRDataBits => site(XLen)
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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case HtifKey => HtifParameters(
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width = Dump("HTIF_WIDTH", 16),
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nSCR = 64,
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offsetBits = site(CacheBlockOffsetBits),
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nCores = site(NTiles))
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//Memory Parameters
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case PAddrBits => 32
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case PgIdxBits => 12
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@ -50,9 +47,10 @@ class DefaultConfig extends ChiselConfig (
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NASTIDataBits => site(MIFDataBits)
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case NASTIAddrBits => site(PAddrBits)
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case NASTIIdBits => site(MIFTagBits)
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case NastiKey => NastiParameters(
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dataBits = site(MIFDataBits),
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addrBits = site(PAddrBits),
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idBits = site(MIFTagBits))
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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@ -74,8 +72,7 @@ class DefaultConfig extends ChiselConfig (
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case Replacer => () => new RandomReplacement(site(NWays))
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case AmoAluOperandBits => site(XLen)
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//L1InstCache
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case NBTBEntries => 62
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case NRAS => 2
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case BtbKey => BtbParameters()
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//L1DataCache
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case WordBits => site(XLen)
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case StoreDataQueueDepth => 17
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@ -86,15 +83,19 @@ class DefaultConfig extends ChiselConfig (
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" })
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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//Tile Constants
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case BuildTiles => {
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TestGeneration.addSuites(rv64i.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
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TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
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List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) }
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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}
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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@ -108,12 +109,11 @@ class DefaultConfig extends ChiselConfig (
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case FastLoadByte => false
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case FastMulDiv => true
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case XLen => 64
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case NMultXpr => 32
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case BuildFPU => {
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val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
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if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
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else TestGeneration.addSuites(env.map(rv64ufNoDiv))
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Some(() => Module(new FPU))
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Some((p: Parameters) => Module(new FPU()(p)))
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}
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case FDivSqrt => true
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case SFMALatency => 2
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@ -124,41 +124,34 @@ class DefaultConfig extends ChiselConfig (
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case NCustomMRWCSRs => 0
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLNManagers) + site(TLNClients)
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case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
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case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLNClients => site(TLNCachingClients) + site(TLNCachelessClients)
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case TLDataBits => site(CacheBlockBytes)*8/site(TLDataBeats)
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case TLDataBeats => 4
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case TLWriteMaskBits => (site(TLDataBits) - 1) / 8 + 1
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case TLNetworkIsOrderedP2P => false
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case TLNManagers => findBy(TLId)
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case TLNCachingClients => findBy(TLId)
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case TLNCachelessClients => findBy(TLId)
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case TLCoherencePolicy => findBy(TLId)
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case TLMaxManagerXacts => findBy(TLId)
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case TLMaxClientXacts => findBy(TLId)
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case TLMaxClientsPerPort => findBy(TLId)
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case "L1ToL2" => {
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case TLNManagers => site(NBanksPerMemoryChannel)*site(NMemoryChannels)
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case TLNCachingClients => site(NTiles)
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case TLNCachelessClients => site(NTiles) + 1
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case TLCoherencePolicy => new MESICoherence(site(L2DirectoryRepresentation))
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case TLMaxManagerXacts => site(NAcquireTransactors) + 2
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case TLMaxClientXacts => max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts))
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case TLMaxClientsPerPort => if(site(BuildRoCC).isEmpty) 1 else 3
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}:PF
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case "L2ToMC" => {
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case TLNManagers => 1
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case TLNCachingClients => site(NBanksPerMemoryChannel)
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case TLNCachelessClients => 0
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case TLCoherencePolicy => new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel)))
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case TLMaxManagerXacts => 1
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case TLMaxClientXacts => 1
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case TLMaxClientsPerPort => site(NAcquireTransactors) + 2
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}:PF
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
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nCachingClients = site(NTiles),
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nCachelessClients = site(NTiles) + 1,
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maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts)),
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maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
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dataBits = site(CacheBlockBytes)*8)()
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
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dataBits = site(CacheBlockBytes)*8)()
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case TLKey("Outermost") => site(TLKey("L2toMC"))
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case NTiles => Knob("NTILES")
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case NMemoryChannels => 1
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case NBanksPerMemoryChannel => Knob("NBANKS")
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@ -169,15 +162,10 @@ class DefaultConfig extends ChiselConfig (
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case UseBackupMemoryPort => true
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case MMIOBase => BigInt(1 << 30) // 1 GB
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case ExternalIOStart => 2 * site(MMIOBase)
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case NASTIAddrMap => Seq(
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("mem", None, MemSize(site(MMIOBase), AddrMap.RWX)),
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("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase),
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genCsrAddrMap())),
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("io", Some(site(ExternalIOStart)),
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MemSize(2 * site(MMIOBase), AddrMap.RW)))
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case NASTIAddrHashMap => new AddrHashMap(site(NASTIAddrMap))
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case NASTINMasters => site(TLNManagers) + 1
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case NASTINSlaves => site(NASTIAddrHashMap).nEntries
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case GlobalAddrMap => AddrMap(
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AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)),
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AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
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AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
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}},
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knobValues = {
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case "NTILES" => 1
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@ -209,16 +197,16 @@ class WithL2Cache extends ChiselConfig(
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site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLDataBits)
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case RowBits => site(TLKey(site(TLId))).dataBits
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2HellaCacheBank, {
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheName => "L2Bank"
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case InnerTLId => "L1ToL2"
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case OuterTLId => "L2ToMC"})
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
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)
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@ -240,7 +228,7 @@ class WithZscale extends ChiselConfig(
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case BuildZscale => {
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TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
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TestGeneration.addSuites(List(zscaleBmarks))
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(r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
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(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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case UseZscale => true
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case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
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@ -264,7 +252,7 @@ class SmallConfig extends ChiselConfig (
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case BuildFPU => None
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case FastMulDiv => false
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case NTLBEntries => 4
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case NBTBEntries => 8
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case BtbKey => BtbParameters(nEntries = 8)
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}},
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knobValues = {
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case "L1D_SETS" => 64
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@ -26,12 +26,13 @@ import uncore._
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* each channel on the manager side of the network
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*/
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abstract class RocketChipNetwork(
|
||||
addrToManagerId: UInt => UInt,
|
||||
sharerToClientId: UInt => UInt,
|
||||
clientDepths: TileLinkDepths,
|
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managerDepths: TileLinkDepths) extends TLModule {
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val nClients = params(TLNClients)
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val nManagers = params(TLNManagers)
|
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addrToManagerId: UInt => UInt,
|
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sharerToClientId: UInt => UInt,
|
||||
clientDepths: TileLinkDepths,
|
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managerDepths: TileLinkDepths)
|
||||
(implicit p: Parameters) extends TLModule()(p) {
|
||||
val nClients = tlNClients
|
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val nManagers = tlNManagers
|
||||
val io = new Bundle {
|
||||
val clients = Vec(new ClientTileLinkIO, nClients).flip
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val managers = Vec(new ManagerTileLinkIO, nManagers).flip
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@ -39,21 +40,21 @@ abstract class RocketChipNetwork(
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||||
|
||||
val clients = io.clients.zipWithIndex.map {
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||||
case (c, i) => {
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val p = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
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val q = Module(new TileLinkEnqueuer(clientDepths))
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p.io.client <> c
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q.io.client <> p.io.network
|
||||
q.io.manager
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val port = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
|
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val qs = Module(new TileLinkEnqueuer(clientDepths))
|
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port.io.client <> c
|
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qs.io.client <> port.io.network
|
||||
qs.io.manager
|
||||
}
|
||||
}
|
||||
|
||||
val managers = io.managers.zipWithIndex.map {
|
||||
case (m, i) => {
|
||||
val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
|
||||
val q = Module(new TileLinkEnqueuer(managerDepths))
|
||||
p.io.manager <> m
|
||||
p.io.network <> q.io.manager
|
||||
q.io.client
|
||||
val port = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
|
||||
val qs = Module(new TileLinkEnqueuer(managerDepths))
|
||||
port.io.manager <> m
|
||||
port.io.network <> qs.io.manager
|
||||
qs.io.client
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -61,10 +62,11 @@ abstract class RocketChipNetwork(
|
||||
/** A simple arbiter for each channel that also deals with header-based routing.
|
||||
* Assumes a single manager agent. */
|
||||
class RocketChipTileLinkArbiter(
|
||||
sharerToClientId: UInt => UInt = (u: UInt) => u,
|
||||
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
|
||||
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
|
||||
extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)
|
||||
sharerToClientId: UInt => UInt = (u: UInt) => u,
|
||||
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
|
||||
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
|
||||
(implicit p: Parameters)
|
||||
extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)(p)
|
||||
with TileLinkArbiterLike
|
||||
with PassesId {
|
||||
val arbN = nClients
|
||||
@ -86,13 +88,14 @@ class RocketChipTileLinkArbiter(
|
||||
* port id are done automatically.
|
||||
*/
|
||||
class RocketChipTileLinkCrossbar(
|
||||
addrToManagerId: UInt => UInt = u => UInt(0),
|
||||
sharerToClientId: UInt => UInt = u => u,
|
||||
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
|
||||
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
|
||||
extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths) {
|
||||
val n = params(LNEndpoints)
|
||||
val count = params(TLDataBeats)
|
||||
addrToManagerId: UInt => UInt = u => UInt(0),
|
||||
sharerToClientId: UInt => UInt = u => u,
|
||||
clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
|
||||
managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
|
||||
(implicit p: Parameters)
|
||||
extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
|
||||
val n = p(LNEndpoints)
|
||||
val count = tlDataBeats
|
||||
// Actually instantiate the particular networks required for TileLink
|
||||
val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
|
||||
val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))
|
||||
|
||||
@ -23,27 +23,31 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
|
||||
/** Whether to use the slow backup memory port [VLSI] */
|
||||
case object UseBackupMemoryPort extends Field[Boolean]
|
||||
/** Function for building some kind of coherence manager agent */
|
||||
case object BuildL2CoherenceManager extends Field[() => CoherenceAgent]
|
||||
case object BuildL2CoherenceManager extends Field[Parameters => CoherenceAgent]
|
||||
/** Function for building some kind of tile connected to a reset signal */
|
||||
case object BuildTiles extends Field[Seq[(Bool) => Tile]]
|
||||
case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
|
||||
/** Start address of the "io" region in the memory map */
|
||||
case object ExternalIOStart extends Field[BigInt]
|
||||
|
||||
/** Utility trait for quick access to some relevant parameters */
|
||||
trait TopLevelParameters extends UsesParameters {
|
||||
val htifW = params(HTIFWidth)
|
||||
val nTiles = params(NTiles)
|
||||
val nMemChannels = params(NMemoryChannels)
|
||||
val nBanksPerMemChannel = params(NBanksPerMemoryChannel)
|
||||
val nBanks = nMemChannels*nBanksPerMemChannel
|
||||
val lsb = params(BankIdLSB)
|
||||
val nMemReqs = params(NOutstandingMemReqsPerChannel)
|
||||
val mifAddrBits = params(MIFAddrBits)
|
||||
val mifDataBeats = params(MIFDataBeats)
|
||||
val scrAddrBits = log2Up(params(HTIFNSCR))
|
||||
val pcrAddrBits = 12
|
||||
val xLen = params(XLen)
|
||||
require(lsb + log2Up(nBanks) < mifAddrBits)
|
||||
trait HasTopLevelParameters {
|
||||
implicit val p: Parameters
|
||||
lazy val nTiles = p(NTiles)
|
||||
lazy val htifW = p(HtifKey).width
|
||||
lazy val csrAddrBits = 12
|
||||
lazy val nMemChannels = p(NMemoryChannels)
|
||||
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
|
||||
lazy val nBanks = nMemChannels*nBanksPerMemChannel
|
||||
lazy val lsb = p(BankIdLSB)
|
||||
lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
|
||||
lazy val mifAddrBits = p(MIFAddrBits)
|
||||
lazy val mifDataBeats = p(MIFDataBeats)
|
||||
lazy val xLen = p(XLen)
|
||||
lazy val nSCR = p(HtifKey).nSCR
|
||||
lazy val scrAddrBits = log2Up(nSCR)
|
||||
lazy val scrDataBits = 64
|
||||
lazy val scrDataBytes = scrDataBits / 8
|
||||
//require(lsb + log2Up(nBanks) < mifAddrBits)
|
||||
}
|
||||
|
||||
class MemBackupCtrlIO extends Bundle {
|
||||
@ -54,28 +58,30 @@ class MemBackupCtrlIO extends Bundle {
|
||||
}
|
||||
|
||||
/** Top-level io for the chip */
|
||||
class BasicTopIO extends Bundle {
|
||||
val host = new HostIO
|
||||
class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
|
||||
with HasTopLevelParameters {
|
||||
val host = new HostIO(htifW)
|
||||
val mem_backup_ctrl = new MemBackupCtrlIO
|
||||
}
|
||||
|
||||
class TopIO extends BasicTopIO {
|
||||
class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
|
||||
val mem = new MemIO
|
||||
}
|
||||
|
||||
class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
|
||||
val mem = Vec(new NASTIIO, nMemChannels)
|
||||
val mmio = new NASTIIO
|
||||
class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
|
||||
val mem = Vec(new NastiIO, nMemChannels)
|
||||
val mmio = new NastiIO
|
||||
}
|
||||
|
||||
/** Top-level module for the chip */
|
||||
//TODO: Remove this wrapper once multichannel DRAM controller is provided
|
||||
class Top extends Module with TopLevelParameters {
|
||||
class Top extends Module with HasTopLevelParameters {
|
||||
implicit val p = params
|
||||
val io = new TopIO
|
||||
if(!params(UseZscale)) {
|
||||
if(!p(UseZscale)) {
|
||||
val temp = Module(new MultiChannelTop)
|
||||
val arb = Module(new NASTIArbiter(nMemChannels))
|
||||
val conv = Module(new MemIONASTIIOConverter(params(CacheBlockOffsetBits)))
|
||||
val arb = Module(new NastiArbiter(nMemChannels))
|
||||
val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
|
||||
arb.io.master <> temp.io.mem
|
||||
conv.io.nasti <> arb.io.slave
|
||||
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
|
||||
@ -85,7 +91,7 @@ class Top extends Module with TopLevelParameters {
|
||||
io.host <> temp.io.host
|
||||
|
||||
// tie off the mmio port
|
||||
val errslave = Module(new NASTIErrorSlave)
|
||||
val errslave = Module(new NastiErrorSlave)
|
||||
errslave.io <> temp.io.mmio
|
||||
} else {
|
||||
val temp = Module(new ZscaleTop)
|
||||
@ -93,23 +99,24 @@ class Top extends Module with TopLevelParameters {
|
||||
}
|
||||
}
|
||||
|
||||
class MultiChannelTop extends Module with TopLevelParameters {
|
||||
class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
|
||||
val io = new MultiChannelTopIO
|
||||
|
||||
// Build an Uncore and a set of Tiles
|
||||
val uncore = Module(new Uncore, {case TLId => "L1ToL2"})
|
||||
val tileList = uncore.io.htif zip params(BuildTiles) map { case(hl, bt) => bt(hl.reset) }
|
||||
val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
|
||||
val uncore = Module(new Uncore()(innerTLParams))
|
||||
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
|
||||
|
||||
// Connect each tile to the HTIF
|
||||
uncore.io.htif.zip(tileList).zipWithIndex.foreach {
|
||||
case ((hl, tile), i) =>
|
||||
tile.io.host.id := UInt(i)
|
||||
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
|
||||
tile.io.host.pcr.req <> Queue(hl.pcr.req)
|
||||
hl.pcr.resp <> Queue(tile.io.host.pcr.resp)
|
||||
tile.io.host.csr.req <> Queue(hl.csr.req)
|
||||
hl.csr.resp <> Queue(tile.io.host.csr.resp)
|
||||
hl.ipi_req <> Queue(tile.io.host.ipi_req)
|
||||
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
|
||||
hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
|
||||
hl.debug_stats_csr := tile.io.host.debug_stats_csr
|
||||
}
|
||||
|
||||
// Connect the uncore to the tile memory ports, HostIO and MemIO
|
||||
@ -118,7 +125,7 @@ class MultiChannelTop extends Module with TopLevelParameters {
|
||||
io.host <> uncore.io.host
|
||||
io.mem <> uncore.io.mem
|
||||
io.mmio <> uncore.io.mmio
|
||||
if(params(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
|
||||
if(p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
|
||||
}
|
||||
|
||||
/** Wrapper around everything that isn't a Tile.
|
||||
@ -126,18 +133,18 @@ class MultiChannelTop extends Module with TopLevelParameters {
|
||||
* Usually this is clocked and/or place-and-routed separately from the Tiles.
|
||||
* Contains the Host-Target InterFace module (HTIF).
|
||||
*/
|
||||
class Uncore extends Module with TopLevelParameters {
|
||||
class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
|
||||
val io = new Bundle {
|
||||
val host = new HostIO
|
||||
val mem = Vec(new NASTIIO, nMemChannels)
|
||||
val host = new HostIO(htifW)
|
||||
val mem = Vec(new NastiIO, nMemChannels)
|
||||
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
|
||||
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
|
||||
val htif = Vec(new HTIFIO, nTiles).flip
|
||||
val htif = Vec(new HtifIO, nTiles).flip
|
||||
val mem_backup_ctrl = new MemBackupCtrlIO
|
||||
val mmio = new NASTIIO
|
||||
val mmio = new NastiIO
|
||||
}
|
||||
|
||||
val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
|
||||
val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
|
||||
val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
|
||||
outmemsys.io.incoherent := htif.io.cpu.map(_.reset)
|
||||
outmemsys.io.htif_uncached <> htif.io.mem
|
||||
@ -149,28 +156,27 @@ class Uncore extends Module with TopLevelParameters {
|
||||
io.htif(i).id := htif.io.cpu(i).id
|
||||
htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
|
||||
io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
|
||||
htif.io.cpu(i).debug_stats_pcr <> io.htif(i).debug_stats_pcr
|
||||
htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
|
||||
|
||||
val pcr_arb = Module(new SMIArbiter(2, 64, 12))
|
||||
pcr_arb.io.in(0) <> htif.io.cpu(i).pcr
|
||||
pcr_arb.io.in(1) <> outmemsys.io.pcr(i)
|
||||
io.htif(i).pcr <> pcr_arb.io.out
|
||||
val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))
|
||||
csr_arb.io.in(0) <> htif.io.cpu(i).csr
|
||||
csr_arb.io.in(1) <> outmemsys.io.csr(i)
|
||||
io.htif(i).csr <> csr_arb.io.out
|
||||
}
|
||||
|
||||
// Arbitrate SCR access between MMIO and HTIF
|
||||
val scrArb = Module(new SMIArbiter(2, 64, scrAddrBits))
|
||||
val scrFile = Module(new SCRFile)
|
||||
|
||||
val scrArb = Module(new SMIArbiter(2, scrDataBits, scrAddrBits))
|
||||
scrArb.io.in(0) <> htif.io.scr
|
||||
scrArb.io.in(1) <> outmemsys.io.scr
|
||||
scrFile.io.smi <> scrArb.io.out
|
||||
// scrFile.io.scr <> (... your SCR connections ...)
|
||||
|
||||
// Wire the htif to the memory port(s) and host interface
|
||||
io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
|
||||
io.host.debug_stats_csr := htif.io.host.debug_stats_csr
|
||||
io.mem <> outmemsys.io.mem
|
||||
io.mmio <> outmemsys.io.mmio
|
||||
if(params(UseBackupMemoryPort)) {
|
||||
if(p(UseBackupMemoryPort)) {
|
||||
outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
|
||||
VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
|
||||
outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
|
||||
@ -183,18 +189,18 @@ class Uncore extends Module with TopLevelParameters {
|
||||
/** The whole outer memory hierarchy, including a NoC, some kind of coherence
|
||||
* manager agent, and a converter from TileLink to MemIO.
|
||||
*/
|
||||
class OuterMemorySystem extends Module with TopLevelParameters {
|
||||
class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters {
|
||||
val io = new Bundle {
|
||||
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
|
||||
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
|
||||
val htif_uncached = (new ClientUncachedTileLinkIO).flip
|
||||
val incoherent = Vec(Bool(), nTiles).asInput
|
||||
val mem = Vec(new NASTIIO, nMemChannels)
|
||||
val mem = Vec(new NastiIO, nMemChannels)
|
||||
val mem_backup = new MemSerializedIO(htifW)
|
||||
val mem_backup_en = Bool(INPUT)
|
||||
val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles)
|
||||
val csr = Vec(new SMIIO(xLen, csrAddrBits), nTiles)
|
||||
val scr = new SMIIO(xLen, scrAddrBits)
|
||||
val mmio = new NASTIIO
|
||||
val mmio = new NastiIO
|
||||
}
|
||||
|
||||
// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
|
||||
@ -211,7 +217,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
|
||||
|
||||
// Create point(s) of coherence serialization
|
||||
val nManagers = nMemChannels * nBanksPerMemChannel
|
||||
val managerEndpoints = List.fill(nManagers) { params(BuildL2CoherenceManager)()}
|
||||
val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)(p)}
|
||||
managerEndpoints.foreach { _.incoherent := io.incoherent }
|
||||
|
||||
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
|
||||
@ -220,27 +226,26 @@ class OuterMemorySystem extends Module with TopLevelParameters {
|
||||
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL)
|
||||
|
||||
// Create a converter between TileLinkIO and MemIO for each channel
|
||||
val outerTLParams = params.alterPartial({ case TLId => "L2ToMC" })
|
||||
val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
|
||||
val backendBuffering = TileLinkDepths(0,0,0,0,0)
|
||||
|
||||
val addrMap = params(NASTIAddrHashMap)
|
||||
val addrMap = p(GlobalAddrMap)
|
||||
val addrHashMap = new AddrHashMap(addrMap)
|
||||
val nMasters = managerEndpoints.size + 1
|
||||
val nSlaves = addrHashMap.nEntries
|
||||
|
||||
println("Generated Address Map")
|
||||
for ((name, base, size, _) <- addrMap.sortedEntries) {
|
||||
for ((name, base, size, _) <- addrHashMap.sortedEntries) {
|
||||
println(f"\t$name%s $base%x - ${base + size - 1}%x")
|
||||
}
|
||||
|
||||
val interconnect = Module(new NASTITopInterconnect)
|
||||
val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves, addrMap)(p))
|
||||
|
||||
for ((bank, i) <- managerEndpoints.zipWithIndex) {
|
||||
val factor = params(TLDataBits) / params(MIFDataBits)
|
||||
val outermostTLParams = outerTLParams.alterPartial({
|
||||
case TLDataBeats => params(MIFDataBeats)
|
||||
case TLDataBits => params(MIFDataBits)
|
||||
})
|
||||
val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
|
||||
val narrow = Module(new TileLinkIONarrower(factor))(outerTLParams)
|
||||
val conv = Module(new NASTIIOTileLinkIOConverter)(outermostTLParams)
|
||||
val outermostTLParams = p.alterPartial({case TLId => "Outermost"})
|
||||
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
|
||||
val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
|
||||
val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
|
||||
unwrap.io.in <> bank.outerTL
|
||||
narrow.io.in <> unwrap.io.out
|
||||
conv.io.tl <> narrow.io.out
|
||||
@ -252,24 +257,24 @@ class OuterMemorySystem extends Module with TopLevelParameters {
|
||||
|
||||
for (i <- 0 until nTiles) {
|
||||
val csrName = s"conf:csr$i"
|
||||
val csrPort = addrMap(csrName).port
|
||||
val conv = Module(new SMIIONASTIIOConverter(xLen, pcrAddrBits))
|
||||
val csrPort = addrHashMap(csrName).port
|
||||
val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
|
||||
conv.io.nasti <> interconnect.io.slaves(csrPort)
|
||||
io.pcr(i) <> conv.io.smi
|
||||
io.csr(i) <> conv.io.smi
|
||||
}
|
||||
|
||||
val conv = Module(new SMIIONASTIIOConverter(xLen, scrAddrBits))
|
||||
conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
|
||||
val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
|
||||
conv.io.nasti <> interconnect.io.slaves(addrHashMap("conf:scr").port)
|
||||
io.scr <> conv.io.smi
|
||||
|
||||
io.mmio <> interconnect.io.slaves(addrMap("io").port)
|
||||
io.mmio <> interconnect.io.slaves(addrHashMap("io").port)
|
||||
|
||||
val mem_channels = interconnect.io.slaves.take(nMemChannels)
|
||||
|
||||
// Create a SerDes for backup memory port
|
||||
if(params(UseBackupMemoryPort)) {
|
||||
if(p(UseBackupMemoryPort)) {
|
||||
VLSIUtils.doOuterMemorySystemSerdes(
|
||||
mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
|
||||
nMemChannels, params(HTIFWidth), params(CacheBlockOffsetBits))
|
||||
nMemChannels, htifW, p(CacheBlockOffsetBits))
|
||||
} else { io.mem <> mem_channels }
|
||||
}
|
||||
|
||||
@ -7,24 +7,26 @@ import junctions._
|
||||
import uncore._
|
||||
|
||||
class MemDessert extends Module {
|
||||
val io = new MemDesserIO(params(HTIFWidth))
|
||||
val x = Module(new MemDesser(params(HTIFWidth)))
|
||||
implicit val p = params
|
||||
val io = new MemDesserIO(p(HtifKey).width)
|
||||
val x = Module(new MemDesser(p(HtifKey).width))
|
||||
io.narrow <> x.io.narrow
|
||||
io.wide <> x.io.wide
|
||||
}
|
||||
|
||||
object VLSIUtils {
|
||||
def doOuterMemorySystemSerdes(
|
||||
llcs: Seq[NASTIIO],
|
||||
mems: Seq[NASTIIO],
|
||||
llcs: Seq[NastiIO],
|
||||
mems: Seq[NastiIO],
|
||||
backup: MemSerializedIO,
|
||||
en: Bool,
|
||||
nMemChannels: Int,
|
||||
htifWidth: Int,
|
||||
blockOffsetBits: Int) {
|
||||
blockOffsetBits: Int)
|
||||
(implicit p: Parameters) {
|
||||
|
||||
val arb = Module(new NASTIArbiter(nMemChannels))
|
||||
val conv = Module(new MemIONASTIIOConverter(blockOffsetBits))
|
||||
val arb = Module(new NastiArbiter(nMemChannels))
|
||||
val conv = Module(new MemIONastiIOConverter(blockOffsetBits))
|
||||
val mem_serdes = Module(new MemSerdes(htifWidth))
|
||||
|
||||
conv.io.nasti <> arb.io.slave
|
||||
|
||||
@ -9,22 +9,22 @@ import rocket._
|
||||
import zscale._
|
||||
|
||||
case object UseZscale extends Field[Boolean]
|
||||
case object BuildZscale extends Field[(Bool) => Zscale]
|
||||
case object BuildZscale extends Field[(Bool, Parameters) => Zscale]
|
||||
case object BootROMCapacity extends Field[Int]
|
||||
case object DRAMCapacity extends Field[Int]
|
||||
|
||||
class ZscaleSystem extends Module {
|
||||
class ZscaleSystem(implicit p: Parameters) extends Module {
|
||||
val io = new Bundle {
|
||||
val host = new HTIFIO
|
||||
val jtag = new HASTIMasterIO().flip
|
||||
val bootmem = new HASTISlaveIO().flip
|
||||
val dram = new HASTISlaveIO().flip
|
||||
val spi = new HASTISlaveIO().flip
|
||||
val led = new POCIIO
|
||||
val corereset = new POCIIO
|
||||
val host = new HtifIO
|
||||
val jtag = new HastiMasterIO().flip
|
||||
val bootmem = new HastiSlaveIO().flip
|
||||
val dram = new HastiSlaveIO().flip
|
||||
val spi = new HastiSlaveIO().flip
|
||||
val led = new PociIO
|
||||
val corereset = new PociIO
|
||||
}
|
||||
|
||||
val core = params(BuildZscale)(io.host.reset)
|
||||
val core = p(BuildZscale)(io.host.reset, p)
|
||||
|
||||
val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
|
||||
|
||||
@ -36,11 +36,11 @@ class ZscaleSystem extends Module {
|
||||
val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
|
||||
val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
|
||||
|
||||
val xbar = Module(new HASTIXbar(3, Seq(bootmem_afn, sbus_afn)))
|
||||
val sadapter = Module(new HASTISlaveToMaster)
|
||||
val sbus = Module(new HASTIBus(Seq(dram_afn, spi_afn, pbus_afn)))
|
||||
val padapter = Module(new HASTItoPOCIBridge)
|
||||
val pbus = Module(new POCIBus(Seq(led_afn, corereset_afn)))
|
||||
val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn)))
|
||||
val sadapter = Module(new HastiSlaveToMaster)
|
||||
val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn)))
|
||||
val padapter = Module(new HastiToPociBridge)
|
||||
val pbus = Module(new PociBus(Seq(led_afn, corereset_afn)))
|
||||
|
||||
core.io.host <> io.host
|
||||
xbar.io.masters(0) <> io.jtag
|
||||
@ -60,14 +60,14 @@ class ZscaleSystem extends Module {
|
||||
io.corereset <> pbus.io.slaves(1)
|
||||
}
|
||||
|
||||
class ZscaleTop extends Module {
|
||||
class ZscaleTop(implicit p: Parameters) extends Module {
|
||||
val io = new Bundle {
|
||||
val host = new HTIFIO
|
||||
val host = new HtifIO
|
||||
}
|
||||
|
||||
val sys = Module(new ZscaleSystem)
|
||||
val bootmem = Module(new HASTISRAM(params(BootROMCapacity)/4))
|
||||
val dram = Module(new HASTISRAM(params(DRAMCapacity)/4))
|
||||
val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4))
|
||||
val dram = Module(new HastiSRAM(p(DRAMCapacity)/4))
|
||||
|
||||
sys.io.host <> io.host
|
||||
bootmem.io <> sys.io.bootmem
|
||||
|
||||
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit 52e1e91c281a03cd7b2399a0a811ad124749c1c8
|
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Subproject commit b0eece1f613d4aafa3f9cf5470576ffb5110e856
|
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2
zscale
2
zscale
@ -1 +1 @@
|
||||
Subproject commit 461e7ee16bb15144e14c42855bf2ee23abd51806
|
||||
Subproject commit 3338af40491ccfe4b403761d755372c201003e39
|
||||
Loading…
Reference in New Issue
Block a user