riscv/rocket-chip
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Point to correct Chisel commit

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Andrew Waterman committed 2015-10-01 10:31:29 -07:00
1 parent a76f0bf8fb
commit 996670a4a6
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chisel
+1 -1
Submodule chisel updated: ededc302ed...d3e0c01512.
emulator/Makefile
+1
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@@ -7,6 +7,7 @@ sim_dir = .
output_dir = $(sim_dir)/output
BACKEND = c
#CONFIG ?= ZscaleConfig
CONFIG ?= DefaultCPPConfig
include $(base_dir)/Makefrag
fpga-zynq
+1 -1
Submodule fpga-zynq updated: eb82eb8b80...2bf892b5ba.