riscv/rocket-chip
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Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)

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This commit is contained in:
Henry Cook 2015-10-20 15:04:39 -07:00
parent 4346111d2a
commit 3fc630405b
5 changed files with 21 additions and 22 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f
Subproject commit 6a165e8b90f09041e9dce30268da8b827d4fdc8c

20
src/main/scala/Configs.scala
View File

@ -98,8 +98,7 @@ class DefaultConfig extends ChiselConfig (
}
}
case BuildRoCC => None
case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
case RoccNMemChannels => 1
//Rocket Core Constants
case FetchWidth => 1
case RetireWidth => 1
@ -109,18 +108,17 @@ class DefaultConfig extends ChiselConfig (
case FastLoadByte => false
case FastMulDiv => true
case XLen => 64
case BuildFPU => {
case UseFPU => {
val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
else TestGeneration.addSuites(env.map(rv64ufNoDiv))
Some((p: Parameters) => Module(new FPU()(p)))
true
}
case FDivSqrt => true
case SFMALatency => 2
case DFMALatency => 3
case CoreInstBits => 32
case CoreDataBits => site(XLen)
case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
case NCustomMRWCSRs => 0
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
@ -132,13 +130,12 @@ class DefaultConfig extends ChiselConfig (
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nCachingClients = site(NTiles),
nCachelessClients = site(NTiles) + 1,
nCachelessClients = 1 + site(NTiles) *
(1 + (if(site(BuildRoCC).isEmpty) 0 else site(RoccNMemChannels))),
maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
if(site(BuildRoCC).isEmpty) 1
else site(RoCCMaxTaggedMemXacts)),
maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3,
if(site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 2,
maxManagerXacts = site(NAcquireTransactors) + 2,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") =>
TileLinkParameters(
@ -149,7 +146,6 @@ class DefaultConfig extends ChiselConfig (
maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
@ -249,7 +245,7 @@ class DefaultFPGAConfig extends ChiselConfig(new FPGAConfig ++ new DefaultConfig
class SmallConfig extends ChiselConfig (
topDefinitions = { (pname,site,here) => pname match {
case BuildFPU => None
case UseFPU => false
case FastMulDiv => false
case NTLBEntries => 4
case BtbKey => BtbParameters(nEntries = 8)

17
src/main/scala/RocketChip.scala
View File

@ -33,6 +33,8 @@ case object ExternalIOStart extends Field[BigInt]
trait HasTopLevelParameters {
implicit val p: Parameters
lazy val nTiles = p(NTiles)
lazy val nCachedTilePorts = p(TLKey("L1toL2")).nCachingClients
lazy val nUncachedTilePorts = p(TLKey("L1toL2")).nCachelessClients - 1
lazy val htifW = p(HtifKey).width
lazy val csrAddrBits = 12
lazy val nMemChannels = p(NMemoryChannels)
@ -120,8 +122,8 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
}
// Connect the uncore to the tile memory ports, HostIO and MemIO
uncore.io.tiles_cached <> tileList.map(_.io.cached)
uncore.io.tiles_uncached <> tileList.map(_.io.uncached)
uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
io.host <> uncore.io.host
io.mem <> uncore.io.mem
io.mmio <> uncore.io.mmio
@ -133,12 +135,13 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
* Usually this is clocked and/or place-and-routed separately from the Tiles.
* Contains the Host-Target InterFace module (HTIF).
*/
class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
class Uncore(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {
val host = new HostIO(htifW)
val mem = Vec(new NastiIO, nMemChannels)
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val htif = Vec(new HtifIO, nTiles).flip
val mem_backup_ctrl = new MemBackupCtrlIO
val mmio = new NastiIO
@ -191,8 +194,8 @@ class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParamete
*/
class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters {
val io = new Bundle {
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val htif_uncached = (new ClientUncachedTileLinkIO).flip
val incoherent = Vec(Bool(), nTiles).asInput
val mem = Vec(new NastiIO, nMemChannels)

2
uncore

@ -1 +1 @@
Subproject commit 75b9b77c2e5f3971b9213904c329520b10f67694
Subproject commit ef7427eea2cc22bc66076f1b04be4b2b314f9e0c

2
zscale

@ -1 +1 @@
Subproject commit 599fc0644351a28759f351c4be7068e5cbb7b092
Subproject commit d6cc2dc512f93be328578e79798ee13510eb4c72