refactor tilelink params, compiles but ExampleSmallConfig fails
This commit is contained in:
Henry Cook
parent
9d11b64c75
commit
dd5052888d
2
rocket
2
rocket
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@ -1 +1 @@
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Subproject commit 3ced30fd6a4686751e2218c5b268c099851dd179
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Subproject commit a72afc525edac561fb3cc5d7bb7eb0756e8f83d9
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@ -46,7 +46,7 @@ class DefaultConfig extends ChiselConfig (
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log2Up(site(NMemoryChannels)))
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
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case MIFDataBeats => site(TLKey("L2toMC")).dataBits/site(MIFDataBits)
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case NastiKey => NastiParameters(
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dataBits = site(MIFDataBits),
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addrBits = site(PAddrBits),
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@ -83,18 +83,18 @@ class DefaultConfig extends ChiselConfig (
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients))
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1ToL2"
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case OuterTLId => "L2ToMC" })))
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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//Tile Constants
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case BuildTiles => {
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TestGeneration.addSuites(rv64i.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
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TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1ToL2"})))
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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}
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case BuildRoCC => None
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@ -124,41 +124,33 @@ class DefaultConfig extends ChiselConfig (
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case NCustomMRWCSRs => 0
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLNManagers) + site(TLNClients)
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case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
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case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLNClients => site(TLNCachingClients) + site(TLNCachelessClients)
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case TLDataBits => site(CacheBlockBytes)*8/site(TLDataBeats)
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case TLDataBeats => 4
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case TLWriteMaskBits => (site(TLDataBits) - 1) / 8 + 1
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case TLNetworkIsOrderedP2P => false
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case TLNManagers => findBy(TLId)
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case TLNCachingClients => findBy(TLId)
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case TLNCachelessClients => findBy(TLId)
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case TLCoherencePolicy => findBy(TLId)
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case TLMaxManagerXacts => findBy(TLId)
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case TLMaxClientXacts => findBy(TLId)
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case TLMaxClientsPerPort => findBy(TLId)
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case "L1ToL2" => {
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case TLNManagers => site(NBanksPerMemoryChannel)*site(NMemoryChannels)
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case TLNCachingClients => site(NTiles)
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case TLNCachelessClients => site(NTiles) + 1
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case TLCoherencePolicy => new MESICoherence(site(L2DirectoryRepresentation))
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case TLMaxManagerXacts => site(NAcquireTransactors) + 2
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case TLMaxClientXacts => max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts))
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case TLMaxClientsPerPort => if(site(BuildRoCC).isEmpty) 1 else 3
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}:PF
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case "L2ToMC" => {
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case TLNManagers => 1
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case TLNCachingClients => site(NBanksPerMemoryChannel)
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case TLNCachelessClients => 0
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case TLCoherencePolicy => new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel)))
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case TLMaxManagerXacts => 1
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case TLMaxClientXacts => 1
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case TLMaxClientsPerPort => site(NAcquireTransactors) + 2
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}:PF
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
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nCachingClients = site(NTiles),
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nCachelessClients = site(NTiles) + 1,
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maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts)),
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maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
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dataBits = site(CacheBlockBytes)*8)()
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
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dataBits = site(CacheBlockBytes)*8)()
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case NTiles => Knob("NTILES")
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case NMemoryChannels => 1
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case NBanksPerMemoryChannel => Knob("NBANKS")
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@ -204,16 +196,16 @@ class WithL2Cache extends ChiselConfig(
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site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLDataBits)
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case RowBits => site(TLKey(site(TLId))).dataBits
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients))
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheName => "L2Bank"
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case InnerTLId => "L1ToL2"
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case OuterTLId => "L2ToMC"})))
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
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)
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@ -235,7 +227,7 @@ class WithZscale extends ChiselConfig(
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case BuildZscale => {
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TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
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TestGeneration.addSuites(List(zscaleBmarks))
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(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1ToL2"})))
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(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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case UseZscale => true
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case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
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@ -31,8 +31,8 @@ abstract class RocketChipNetwork(
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clientDepths: TileLinkDepths,
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managerDepths: TileLinkDepths)
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(implicit p: Parameters) extends TLModule()(p) {
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val nClients = p(TLNClients)
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val nManagers = p(TLNManagers)
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val nClients = tlNClients
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val nManagers = tlNManagers
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val io = new Bundle {
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val clients = Vec(new ClientTileLinkIO, nClients).flip
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val managers = Vec(new ManagerTileLinkIO, nManagers).flip
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@ -95,7 +95,7 @@ class RocketChipTileLinkCrossbar(
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(implicit p: Parameters)
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extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
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val n = p(LNEndpoints)
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val count = p(TLDataBeats)
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val count = tlDataBeats
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// Actually instantiate the particular networks required for TileLink
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val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
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val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))
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@ -30,9 +30,10 @@ case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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case object ExternalIOStart extends Field[BigInt]
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/** Utility trait for quick access to some relevant parameters */
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trait HasTopLevelParameters extends HasHtifParameters {
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trait HasTopLevelParameters {
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implicit val p: Parameters
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lazy val nTiles = p(NTiles)
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lazy val htifW = w
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lazy val htifW = p(HtifKey).width
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lazy val csrAddrBits = 12
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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@ -42,6 +43,10 @@ trait HasTopLevelParameters extends HasHtifParameters {
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lazy val mifAddrBits = p(MIFAddrBits)
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lazy val mifDataBeats = p(MIFDataBeats)
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lazy val xLen = p(XLen)
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lazy val nSCR = p(HtifKey).nSCR
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lazy val scrAddrBits = log2Up(nSCR)
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lazy val scrDataBits = 64
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lazy val scrDataBytes = scrDataBits / 8
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//require(lsb + log2Up(nBanks) < mifAddrBits)
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}
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@ -55,7 +60,7 @@ class MemBackupCtrlIO extends Bundle {
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/** Top-level io for the chip */
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters {
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val host = new HostIO
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val host = new HostIO(htifW)
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val mem_backup_ctrl = new MemBackupCtrlIO
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}
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@ -98,7 +103,7 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
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val io = new MultiChannelTopIO
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// Build an Uncore and a set of Tiles
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val innerTLParams = p.alterPartial({case TLId => "L1ToL2" })
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val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
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val uncore = Module(new Uncore()(innerTLParams))
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val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
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@ -130,7 +135,7 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
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*/
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class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
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val io = new Bundle {
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val host = new HostIO
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val host = new HostIO(htifW)
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val mem = Vec(new NastiIO, nMemChannels)
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val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
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val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
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@ -221,7 +226,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL)
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// Create a converter between TileLinkIO and MemIO for each channel
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val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" })
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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val addrMap = p(GlobalAddrMap)
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2
uncore
2
uncore
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@ -1 +1 @@
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Subproject commit 69e494348c2b3ea7ff3abed392fcff2fb7cf730c
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Subproject commit 3c742a5a91a4405e1de1fe2d8d86ca8e1ed1bfaf
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