riscv/rocket-chip
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L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)

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This commit is contained in:
Henry Cook 2015-10-16 19:15:47 -07:00
parent c4117eb9a2
commit 8c3370c2e3
4 changed files with 6 additions and 17 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 4d29d5c48cfaa3800bf5b6d5428a9c6e83335477
Subproject commit 3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f

17
src/main/scala/Configs.scala
View File

@ -139,7 +139,7 @@ class DefaultConfig extends ChiselConfig (
maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3,
maxManagerXacts = site(NAcquireTransactors) + 2,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8)()
dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") =>
TileLinkParameters(
coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
@ -150,19 +150,8 @@ class DefaultConfig extends ChiselConfig (
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8)()
case TLKey("Outermost") =>
TileLinkParameters(
coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = 1,
nCachingClients = site(NBanksPerMemoryChannel),
nCachelessClients = 0,
maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8,
dataBeats = site(MIFDataBeats))()
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
case NMemoryChannels => 1
case NBanksPerMemoryChannel => Knob("NBANKS")

2
uncore

@ -1 +1 @@
Subproject commit aa40f7d7c11b5dd099376baf73b998da859a1616
Subproject commit b2d20a8166fe3121f35298adcab2594eda642be6

2
zscale

@ -1 +1 @@
Subproject commit 3338af40491ccfe4b403761d755372c201003e39
Subproject commit 599fc0644351a28759f351c4be7068e5cbb7b092