L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)

src/main/scala/Configs.scala

@@ -139,7 +139,7 @@ class DefaultConfig extends ChiselConfig (
           maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3,
           maxManagerXacts = site(NAcquireTransactors) + 2,
           addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
-          dataBits = site(CacheBlockBytes)*8)()
+          dataBits = site(CacheBlockBytes)*8)
       case TLKey("L2toMC") => 
         TileLinkParameters(
           coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
@@ -150,19 +150,8 @@ class DefaultConfig extends ChiselConfig (
           maxClientsPerPort = site(NAcquireTransactors) + 2,
           maxManagerXacts = 1,
           addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
-          dataBits = site(CacheBlockBytes)*8)()
-      case TLKey("Outermost") =>
-        TileLinkParameters(
-          coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
-          nManagers = 1,
-          nCachingClients = site(NBanksPerMemoryChannel),
-          nCachelessClients = 0,
-          maxClientXacts = 1,
-          maxClientsPerPort = site(NAcquireTransactors) + 2,
-          maxManagerXacts = 1,
-          addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
-          dataBits = site(CacheBlockBytes)*8,
-          dataBeats = site(MIFDataBeats))()
+          dataBits = site(CacheBlockBytes)*8)
+      case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
       case NTiles => Knob("NTILES")
       case NMemoryChannels => 1
       case NBanksPerMemoryChannel => Knob("NBANKS")