Chisel3 compat: merge NASTIMasterIO and NASTISlaveIO so we do not depend on flip() modifying the object
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@ -55,7 +55,7 @@ trait NASTIChannel extends NASTIBundle
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trait NASTIMasterToSlaveChannel extends NASTIChannel
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trait NASTISlaveToMasterChannel extends NASTIChannel
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class NASTIMasterIO extends Bundle {
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class NASTIIO extends Bundle {
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val aw = Decoupled(new NASTIWriteAddressChannel)
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val w = Decoupled(new NASTIWriteDataChannel)
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val b = Decoupled(new NASTIWriteResponseChannel).flip
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@ -63,8 +63,6 @@ class NASTIMasterIO extends Bundle {
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val r = Decoupled(new NASTIReadDataChannel).flip
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}
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class NASTISlaveIO extends NASTIMasterIO { flip() }
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trait HasNASTIMetadata extends NASTIBundle {
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val addr = UInt(width = nastiXAddrBits)
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val len = UInt(width = nastiXLenBits)
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@ -182,9 +180,9 @@ object NASTIWriteResponseChannel {
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}
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}
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class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NASTIParameters {
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class MemIONASTIIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NASTIParameters {
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val io = new Bundle {
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val nasti = new NASTISlaveIO
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val nasti = (new NASTIIO).flip
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val mem = new MemIO
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}
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@ -238,8 +236,8 @@ class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule wi
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/** Arbitrate among arbN masters requesting to a single slave */
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class NASTIArbiter(val arbN: Int) extends NASTIModule {
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val io = new Bundle {
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val master = Vec(new NASTISlaveIO, arbN)
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val slave = new NASTIMasterIO
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val master = Vec(new NASTIIO, arbN).flip
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val slave = new NASTIIO
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}
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if (arbN > 1) {
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@ -346,7 +344,7 @@ class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
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/** A slave that send decode error for every request it receives */
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class NASTIErrorSlave extends NASTIModule {
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val io = new NASTISlaveIO
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val io = (new NASTIIO).flip
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when (io.ar.fire()) { printf("Invalid read address %x\n", io.ar.bits.addr) }
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when (io.aw.fire()) { printf("Invalid write address %x\n", io.aw.bits.addr) }
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@ -401,8 +399,8 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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val nSlaves = addrmap.size
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val io = new Bundle {
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val master = new NASTISlaveIO
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val slave = Vec(new NASTIMasterIO, nSlaves)
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val master = (new NASTIIO).flip
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val slave = Vec(new NASTIIO, nSlaves)
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}
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var ar_ready = Bool(false)
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@ -479,8 +477,8 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
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extends NASTIModule {
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val io = new Bundle {
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val masters = Vec(new NASTISlaveIO, nMasters)
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val slaves = Vec(new NASTIMasterIO, nSlaves)
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val masters = Vec(new NASTIIO, nMasters).flip
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val slaves = Vec(new NASTIIO, nSlaves)
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}
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val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io }
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@ -594,8 +592,8 @@ case object NASTIAddrHashMap extends Field[AddrHashMap]
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class NASTIInterconnectIO(val nMasters: Int, val nSlaves: Int) extends Bundle {
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/* This is a bit confusing. The interconnect is a slave to the masters and
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* a master to the slaves. Hence why the declarations seem to be backwards. */
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val masters = Vec(new NASTISlaveIO, nMasters)
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val slaves = Vec(new NASTIMasterIO, nSlaves)
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val masters = Vec(new NASTIIO, nMasters).flip
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val slaves = Vec(new NASTIIO, nSlaves)
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override def cloneType =
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new NASTIInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
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}
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@ -250,10 +250,10 @@ class SMIIONASTIWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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}
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/** Convert NASTI protocol to SMI protocol */
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class SMIIONASTISlaveIOConverter(val dataWidth: Int, val addrWidth: Int)
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class SMIIONASTIIOConverter(val dataWidth: Int, val addrWidth: Int)
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extends NASTIModule {
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val io = new Bundle {
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val nasti = new NASTISlaveIO
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val nasti = (new NASTIIO).flip
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val smi = new SMIIO(dataWidth, addrWidth)
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}
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