added HasAddrMapParameters and GlobalAddrMap
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Submodule junctions updated: 790f01f9e5...55471be1a8
2
rocket
2
rocket
Submodule rocket updated: dcc32b8e6e...3ced30fd6a
@ -169,7 +169,7 @@ class DefaultConfig extends ChiselConfig (
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case UseBackupMemoryPort => true
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case MMIOBase => BigInt(1 << 30) // 1 GB
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case ExternalIOStart => 2 * site(MMIOBase)
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case NastiAddrMap => AddrMap(
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case GlobalAddrMap => AddrMap(
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AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)),
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AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
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AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
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@ -224,16 +224,17 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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val addrMap = new AddrHashMap(p(NastiAddrMap))
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = new AddrHashMap(addrMap)
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val nMasters = managerEndpoints.size + 1
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val nSlaves = addrMap.nEntries
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val nSlaves = addrHashMap.nEntries
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println("Generated Address Map")
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for ((name, base, size, _) <- addrMap.sortedEntries) {
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for ((name, base, size, _) <- addrHashMap.sortedEntries) {
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println(f"\t$name%s $base%x - ${base + size - 1}%x")
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}
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val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves)(p))
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val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves, addrMap)(p))
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for ((bank, i) <- managerEndpoints.zipWithIndex) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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@ -248,17 +249,17 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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for (i <- 0 until nTiles) {
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val csrName = s"conf:csr$i"
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val csrPort = addrMap(csrName).port
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val csrPort = addrHashMap(csrName).port
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val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
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conv.io.nasti <> interconnect.io.slaves(csrPort)
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io.csr(i) <> conv.io.smi
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}
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val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
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conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
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conv.io.nasti <> interconnect.io.slaves(addrHashMap("conf:scr").port)
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io.scr <> conv.io.smi
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io.mmio <> interconnect.io.slaves(addrMap("io").port)
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io.mmio <> interconnect.io.slaves(addrHashMap("io").port)
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val mem_channels = interconnect.io.slaves.take(nMemChannels)
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2
uncore
2
uncore
Submodule uncore updated: c824028e4f...69e494348c
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