Implement bypassing L1 data cache for MMIO
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@ -4,18 +4,23 @@ package rocket
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import Chisel._
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import uncore._
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import junctions.MMIOBase
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import Util._
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case object WordBits extends Field[Int]
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case object StoreDataQueueDepth extends Field[Int]
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case object ReplayQueueDepth extends Field[Int]
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case object NMSHRs extends Field[Int]
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case object NIOMSHRs extends Field[Int]
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case object LRSCCycles extends Field[Int]
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abstract trait L1HellaCacheParameters extends L1CacheParameters {
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val wordBits = params(WordBits)
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val wordBytes = wordBits/8
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val wordOffBits = log2Up(wordBytes)
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val beatBytes = params(CacheBlockBytes) / params(TLDataBeats)
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val beatWords = beatBytes / wordBytes
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val beatOffBits = log2Up(beatBytes)
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val idxMSB = untagBits-1
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val idxLSB = blockOffBits
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val offsetmsb = idxLSB-1
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@ -26,6 +31,8 @@ abstract trait L1HellaCacheParameters extends L1CacheParameters {
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val encRowBits = encDataBits*rowWords
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val sdqDepth = params(StoreDataQueueDepth)
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val nMSHRs = params(NMSHRs)
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val nIOMSHRs = params(NIOMSHRs)
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val mmioBase = params(MMIOBase)
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}
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abstract class L1HellaCacheBundle extends Bundle with L1HellaCacheParameters
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@ -130,6 +137,83 @@ class WritebackReq extends Release with CacheParameters {
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val way_en = Bits(width = nWays)
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}
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class IOMSHR(id: Int) extends L1HellaCacheModule {
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val io = new Bundle {
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val req = Decoupled(new HellaCacheReq).flip
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val acquire = Decoupled(new Acquire)
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val grant = Valid(new Grant).flip
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val resp = Decoupled(new HellaCacheResp)
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}
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def wordFromBeat(addr: UInt, dat: UInt) = {
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val offset = addr(beatOffBits - 1, wordOffBits)
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val shift = Cat(offset, UInt(0, wordOffBits + 3))
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(dat >> shift)(wordBits - 1, 0)
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}
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val req = Reg(new HellaCacheReq)
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val grant_word = Reg(UInt(width = wordBits))
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val storegen = new StoreGen(req.typ, req.addr, req.data)
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val loadgen = new LoadGen(req.typ, req.addr, grant_word, Bool(false))
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val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
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val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
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val beat_data = Fill(beatWords, storegen.data)
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val addr_byte = req.addr(beatOffBits - 1, 0)
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val a_type = Mux(isRead(req.cmd), Acquire.getType, Acquire.putType)
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val union = Mux(isRead(req.cmd),
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Cat(addr_byte, req.typ, M_XRD), beat_mask)
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val s_idle :: s_acquire :: s_grant :: s_resp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.req.ready := (state === s_idle)
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io.acquire.valid := (state === s_acquire)
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io.acquire.bits := Acquire(
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is_builtin_type = Bool(true),
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a_type = a_type,
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client_xact_id = UInt(id),
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addr_block = req.addr(paddrBits - 1, blockOffBits),
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addr_beat = req.addr(blockOffBits - 1, beatOffBits),
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data = beat_data,
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// alloc bit should always be false
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union = Cat(union, Bool(false)))
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io.resp.valid := (state === s_resp)
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io.resp.bits := req
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io.resp.bits.has_data := isRead(req.cmd)
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io.resp.bits.data := loadgen.word
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io.resp.bits.data_subword := loadgen.byte
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io.resp.bits.store_data := req.data
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io.resp.bits.nack := Bool(false)
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io.resp.bits.replay := io.resp.valid
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when (io.req.fire()) {
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req := io.req.bits
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state := s_acquire
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}
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when (io.acquire.fire()) {
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state := s_grant
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}
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when (state === s_grant && io.grant.valid) {
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when (isRead(req.cmd)) {
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grant_word := wordFromBeat(req.addr, io.grant.bits.data)
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state := s_resp
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} .otherwise {
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state := s_idle
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}
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}
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when (io.resp.fire()) {
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state := s_idle
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}
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}
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class MSHR(id: Int) extends L1HellaCacheModule {
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val io = new Bundle {
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val req_pri_val = Bool(INPUT)
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@ -282,6 +366,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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class MSHRFile extends L1HellaCacheModule {
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val io = new Bundle {
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val req = Decoupled(new MSHRReq).flip
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val resp = Decoupled(new HellaCacheResp)
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val secondary_miss = Bool(OUTPUT)
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val mem_req = Decoupled(new Acquire)
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@ -296,10 +381,13 @@ class MSHRFile extends L1HellaCacheModule {
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val fence_rdy = Bool(OUTPUT)
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}
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// determine if the request is in the memory region or mmio region
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val cacheable = io.req.bits.addr < UInt(mmioBase)
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = io.req.valid && io.req.ready && isWrite(io.req.bits.cmd)
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val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd)
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val sdq = Mem(io.req.bits.data, sdqDepth)
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when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
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@ -313,7 +401,7 @@ class MSHRFile extends L1HellaCacheModule {
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val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
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val mem_req_arb = Module(new LockingArbiter(
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new Acquire,
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nMSHRs,
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nMSHRs + nIOMSHRs,
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outerDataBeats,
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(a: Acquire) => a.hasMultibeatData()))
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val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
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@ -360,14 +448,44 @@ class MSHRFile extends L1HellaCacheModule {
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when (!mshr.io.probe_rdy) { io.probe_rdy := false }
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}
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alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
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alloc_arb.io.out.ready := io.req.valid && sdq_rdy && cacheable && !idx_match
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io.meta_read <> meta_read_arb.io.out
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io.meta_write <> meta_write_arb.io.out
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io.mem_req <> mem_req_arb.io.out
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io.wb_req <> wb_req_arb.io.out
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io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
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val resp_arb = Module(new Arbiter(new HellaCacheResp, nIOMSHRs))
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var mmio_rdy = Bool(false)
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for (i <- 0 until nIOMSHRs) {
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val id = nMSHRs + i
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val mshr = Module(new IOMSHR(id))
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mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
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mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
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mshr.io.req.bits := io.req.bits
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mmio_rdy = mmio_rdy || mshr.io.req.ready
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mem_req_arb.io.in(id) <> mshr.io.acquire
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mshr.io.grant.bits := io.mem_grant.bits
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mshr.io.grant.valid := io.mem_grant.valid &&
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io.mem_grant.bits.client_xact_id === UInt(id)
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resp_arb.io.in(i) <> mshr.io.resp
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when (!mshr.io.req.ready) { io.fence_rdy := Bool(false) }
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}
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mmio_alloc_arb.io.out.ready := io.req.valid && !cacheable
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io.resp <> resp_arb.io.out
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io.req.ready := Mux(!cacheable, mmio_rdy,
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Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy)
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io.secondary_miss := idx_match
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io.refill := refillMux(io.mem_grant.bits.client_xact_id)
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@ -824,7 +942,11 @@ class HellaCache extends L1HellaCacheModule {
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mshrs.io.mem_grant.valid := narrow_grant.fire()
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mshrs.io.mem_grant.bits := narrow_grant.bits
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narrow_grant.ready := writeArb.io.in(1).ready || !narrow_grant.bits.hasData()
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writeArb.io.in(1).valid := narrow_grant.valid && narrow_grant.bits.hasData()
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/* The last clause here is necessary in order to prevent the responses for
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* the IOMSHRs from being written into the data array. It works because the
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* IOMSHR ids start right the ones for the regular MSHRs. */
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writeArb.io.in(1).valid := narrow_grant.valid && narrow_grant.bits.hasData() &&
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narrow_grant.bits.client_xact_id < UInt(nMSHRs)
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writeArb.io.in(1).bits.addr := mshrs.io.refill.addr
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writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en
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writeArb.io.in(1).bits.wmask := ~UInt(0, nWays)
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@ -893,16 +1015,25 @@ class HellaCache extends L1HellaCacheModule {
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io.cpu.req.ready := Bool(false)
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}
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io.cpu.resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
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io.cpu.resp.bits.nack := s2_valid && s2_nack
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io.cpu.resp.bits := s2_req
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io.cpu.resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
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io.cpu.resp.bits.replay := s2_replay
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io.cpu.resp.bits.data := loadgen.word
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io.cpu.resp.bits.data_subword := loadgen.byte | s2_sc_fail
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io.cpu.resp.bits.store_data := s2_req.data
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io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
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val cache_resp = Wire(Valid(new HellaCacheResp))
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cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
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cache_resp.bits := s2_req
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cache_resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
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cache_resp.bits.data := loadgen.word
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cache_resp.bits.data_subword := loadgen.byte | s2_sc_fail
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cache_resp.bits.store_data := s2_req.data
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cache_resp.bits.nack := s2_valid && s2_nack
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cache_resp.bits.replay := s2_replay
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val uncache_resp = Wire(Valid(new HellaCacheResp))
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uncache_resp.bits := mshrs.io.resp.bits
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uncache_resp.valid := mshrs.io.resp.valid
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val cache_pass = s2_valid || s2_replay
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mshrs.io.resp.ready := !cache_pass
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io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)
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io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
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io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
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io.cpu.replay_next.bits := s1_req.tag
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}
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