riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman aee9378712 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Andrew Waterman 7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Andrew Waterman a09e8d1c55 remove I$ prefetcher for now 
there's a bug in it, and I don't have time to fix it at the moment.
 2012-03-27 15:43:56 -07:00
Andrew Waterman 452876af37 fence on vvcfg; implement fence.v.g correctly 2012-03-27 14:49:00 -07:00
Andrew Waterman 6bda8674bd no dessert tonight :( 2012-03-26 23:50:09 -07:00
Andrew Waterman e2fe525fb6 remove bug from dessert 2012-03-26 14:18:57 -07:00
Andrew Waterman 5f53cd4ac1 reduce HTIF width 2012-03-25 23:49:59 -07:00
Andrew Waterman ef505de017 reduce HTIF width 2012-03-25 23:49:45 -07:00
Andrew Waterman 31f0b600fd add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman 1666d3fbd7 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman f62a02ab54 remove dumb stuff in top.scala 2012-03-25 21:30:01 -07:00
Andrew Waterman 88bf8a4f23 add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman 7fa93da4f5 add backup memory port (disabled for now) 2012-03-25 15:49:32 -07:00
Andrew Waterman 86d56ff67b refactor cpu/i$/d$ into Tile (rather than Top) 2012-03-24 16:57:28 -07:00
Andrew Waterman 3a487ac89b improve htif<->pcr interface 2012-03-24 16:57:28 -07:00
Andrew Waterman 54fa6f660d new supervisor mode 2012-03-24 13:03:31 -07:00
Andrew Waterman bd27d0fab2 can now take interrupts on stalled instructions 2012-03-19 01:02:06 -07:00
Andrew Waterman 2ed0be65f9 fix RRArbiter 2012-03-19 00:19:33 -07:00
Andrew Waterman c4a91303fb update vector fence names and encoding 2012-03-18 20:42:38 -07:00
Andrew Waterman a47eeb9571 retime D$ bypass into beginning of EX stage 2012-03-16 18:35:54 -07:00
Andrew Waterman 6c26921766 reduce D$ critical path through page table walker 
costs an extra cycle per page table level to resolve a TLB miss. too bad.
 2012-03-16 18:35:54 -07:00
Andrew Waterman f0157b9e2a fix coherence bug 
popping wrong store dependence queue
 2012-03-16 01:24:07 -07:00
Andrew Waterman cfca2d1411 clean up cache interfaces; avoid reserved keywords 2012-03-16 00:44:16 -07:00
Andrew Waterman 820884c7e6 fix probes for smaller cache sizes 
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
 2012-03-15 23:08:30 -07:00
Andrew Waterman 4684171ac6 fix fence.i for associative caches 2012-03-15 21:23:21 -07:00
Andrew Waterman 2b0bc8df2b use divided clk for htif. UDPATE YOUR FESVR 
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
 2012-03-15 18:36:51 -07:00
Andrew Waterman 7dde7099d2 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Andrew Waterman ab6c9350db fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman 1788c34113 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman 1492457df5 add probe replies to HTIF 2012-03-13 16:56:47 -07:00
Andrew Waterman b0f798962c add probe unit 2012-03-13 16:43:51 -07:00
Andrew Waterman d76b05bde1 fix way selection on D$ write upgrades 2012-03-13 02:21:02 -07:00
Andrew Waterman fd29e00db0 support non-power-of-2 queue sizes 
need to manually wrap queue pointers.
 2012-03-13 01:58:28 -07:00
Andrew Waterman 8ffdac9526 fix D$ store-upgrade bug 
loads to the same address as stores that cause an upgrade
could return the old value
 2012-03-10 15:50:10 -08:00
Andrew Waterman 4f4b990a4f fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Andrew Waterman 7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00
Andrew Waterman e3a68848e0 fix D$ critical paths and fix verilog build 2012-03-09 20:02:51 -08:00
Andrew Waterman 85504f0ddc fix bug in fence.i and improve test 2012-03-09 03:26:05 -08:00
Andrew Waterman 766bac88f8 refactor D$ writebacks and flushes 
MSHRs now arbitrate for writebacks and handle flushes.
 2012-03-09 02:55:46 -08:00
Andrew Waterman ff2e47f380 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman 5a7c5772a8 clearly distinguish PPN and cache tag 2012-03-07 23:11:17 -08:00
Andrew Waterman 941873bad1 coherence hub fixes 2012-03-07 21:03:44 -08:00
Andrew Waterman c09eeb7fd2 fix D$ next-state logic 
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
 2012-03-07 01:42:08 -08:00
Andrew Waterman a0c9452b86 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Andrew Waterman 6e2610b0ad fix Mux1H for bundles 2012-03-06 23:38:36 -08:00
Andrew Waterman 499c5b4a2e automatically infer MEM_TAG_BITS 2012-03-06 15:49:28 -08:00
Andrew Waterman 6e16b04ada implement transaction finish messages 2012-03-06 15:48:08 -08:00
Andrew Waterman 5f33ab24b0 fix merge conflict 
oops :(
 2012-03-06 02:02:53 -08:00
Andrew Waterman 5f12990dfb support memory transaction aborts 2012-03-06 00:35:02 -08:00
Andrew Waterman 1e1926ce63 flip direction of ioPipe to match ioDecoupled 2012-03-02 16:18:32 -08:00
Andrew Waterman 6d03d75835 improve D$ internal interfaces 2012-03-01 20:20:15 -08:00
Andrew Waterman 28cacd953f D$ cleanup - merge ReplayUnit and MSHRFile 2012-03-01 19:30:56 -08:00
Andrew Waterman 52101373e0 clean up D$ store data unit 2012-03-01 19:20:00 -08:00
Andrew Waterman c38065d0e8 clean up priority encoders 2012-02-29 16:13:14 -08:00
Andrew Waterman b9ec69f8f5 add new Queue singleton 2012-02-29 14:21:42 -08:00
Andrew Waterman 012da6002e replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Andrew Waterman c99f6bbeb7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Andrew Waterman 2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman 1d41a41afa remove extraneous constants 2012-02-27 17:49:48 -08:00
Andrew Waterman 6e706c7c74 fix yet another AMO-related replay bug 2012-02-26 20:20:45 -08:00
Andrew Waterman e12b9eae93 remove ext_mem interface 
hindsight is 20/20
 2012-02-26 18:53:39 -08:00
Andrew Waterman 2d04664a98 simplify cpu-cache interface 2012-02-26 18:26:29 -08:00
Andrew Waterman ad713a5d83 fix icache ram depth; new chisel 2012-02-26 17:51:46 -08:00
Andrew Waterman 4121fb178c clean up mul/div interface; use VU mul if HAVE_VEC 2012-02-24 19:22:35 -08:00
Andrew Waterman b3a3289d34 fix (?) external memory request nack interface 2012-02-24 01:42:33 -08:00
Andrew Waterman 7b3cce79e3 allocate a primary miss on a prefetch 2012-02-23 22:40:24 -08:00
Andrew Waterman 012028efaa fix fpga build 2012-02-23 22:19:38 -08:00
Andrew Waterman 5332bab6f1 expose FMA ports outside of FPU (for the VU) 2012-02-23 17:39:34 -08:00
Andrew Waterman 6ceaa0e80a correct and simplify replay_next logic 2012-02-23 16:52:52 -08:00
Andrew Waterman f939088be1 move datapath control signals into control unit 
because that's where control signals go
 2012-02-23 16:52:52 -08:00
Andrew Waterman 7c929afe2b HTIF now controls CPU reset 2012-02-22 19:30:03 -08:00
Andrew Waterman 3eebf40310 nack CPU requests during any replay 2012-02-22 18:37:13 -08:00
Andrew Waterman cfd79c731b add resp_type to ext_mem interface 2012-02-21 17:42:00 -08:00
Andrew Waterman 9a80adef50 only instantiate VI$ if HAVE_VEC 2012-02-21 15:53:19 -08:00
Andrew Waterman c8f768c8b3 fix AMO replay bug 
like the recent AMO bug fix, but affects stores too.  oops.
 2012-02-21 14:39:54 -08:00
Andrew Waterman d5608b2728 fix AMO replay bug 
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
 2012-02-21 01:02:16 -08:00
Andrew Waterman 6135615104 unify cache backend interfaces; generify arbiter 2012-02-20 00:51:48 -08:00
Andrew Waterman 7034c9be65 new htif protocol and implementation 
You must update your fesvr and isasim!
 2012-02-19 23:15:45 -08:00
Andrew Waterman 9af86633d7 invalidate I$ prefetcher when invalidating I$ 2012-02-17 17:56:01 -08:00
Andrew Waterman 1b5e39e7fc fix bug in BTB 
a BTB update followed by a taken branch could cause incorrect control flow.
 2012-02-15 21:36:08 -08:00
Andrew Waterman fc5ba769da disable vector unit by default 2012-02-15 18:58:41 -08:00
Andrew Waterman 8b3b3abd3d fix external memory request nack logic 2012-02-15 18:57:40 -08:00
Andrew Waterman fe2c1d1321 add vec->ctrl fences 2012-02-15 18:31:19 -08:00
Andrew Waterman c13524ad3a fix vcmdq full replay logic 2012-02-15 17:49:12 -08:00
Andrew Waterman 0ec7767c13 declaring success on FPU for now 2012-02-14 19:11:57 -08:00
Andrew Waterman 297223a13c squash subsequent external mem request after nack 2012-02-14 15:12:16 -08:00
Andrew Waterman 38c67e5a9e add fmin.[s|d] and fmax.[s|d] 2012-02-14 06:37:18 -08:00
Andrew Waterman ee9fc10668 add fcvt.s.d, fcvt.d.s 2012-02-14 06:03:43 -08:00
Andrew Waterman ce202c73d1 add fsgnj[n|x].[s|d] 2012-02-14 04:24:35 -08:00
Andrew Waterman 1d604bcd49 remove top-level Makefile 
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
 2012-02-14 02:53:43 -08:00
Andrew Waterman 15dc2d8c40 add fp writeback arbitration logic 2012-02-14 00:32:25 -08:00
Andrew Waterman 0366465cb1 parameterize the scoreboards 2012-02-13 18:12:23 -08:00
Andrew Waterman 6c2d8a37ae remove a partial update that makes chisel barf 
chisel regards it as a combinational loop, even though it isn't.
 2012-02-13 16:45:29 -08:00
Andrew Waterman c78c738f60 minor cleanups 2012-02-13 03:13:49 -08:00
Andrew Waterman b5a19a54a3 add fcvt.[s|d].[w|l][u] 2012-02-13 02:01:26 -08:00
Andrew Waterman a4a9d2312c add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d] 2012-02-13 01:30:01 -08:00
Andrew Waterman 069037ff3a add FP recoding 2012-02-12 23:31:50 -08:00
Andrew Waterman 25ecfb9bbc clean up caches 
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
 2012-02-12 20:32:06 -08:00
Andrew Waterman 08b6517a23 add FP ops mftx, mxtf, mtfsr, mffsr 2012-02-12 20:12:53 -08:00
Andrew Waterman 9bb1558a34 WIP on FPU 2012-02-12 04:36:01 -08:00