riscv/rocket-chip
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clean up priority encoders

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This commit is contained in:
Andrew Waterman 2012-02-29 16:13:14 -08:00
parent b9ec69f8f5
commit c38065d0e8
4 changed files with 16 additions and 58 deletions
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11
rocket/src/main/scala/dtlb.scala
View File

@ -118,12 +118,9 @@ class rocketDTLB(entries: Int) extends Component
}
// high if there are any unused (invalid) entries in the TLB
val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries));
val ie_enc = new priorityEncoder(entries);
ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix;
val ie_addr = ie_enc.io.out;
val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
val has_invalid_entry = !tag_cam.io.valid_bits.andR
val invalid_entry = PriorityEncoder(~tag_cam.io.valid_bits)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, repl_count).toUFix;
val lookup = (state === s_ready) && r_cpu_req_val && !io.cpu_req.bits.kill && (req_load || req_store || req_amo || req_pf);
val lookup_hit = lookup && tag_hit;
@ -136,7 +133,7 @@ class rocketDTLB(entries: Int) extends Component
when (tlb_miss) {
r_refill_tag := lookup_tag;
r_refill_waddr := repl_waddr;
when (!invalid_entry) {
when (!has_invalid_entry) {
repl_count := repl_count + UFix(1);
}
}

11
rocket/src/main/scala/itlb.scala
View File

@ -146,12 +146,9 @@ class rocketITLB(entries: Int) extends Component
}
// high if there are any unused entries in the ITLB
val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries));
val ie_enc = new priorityEncoder(entries);
ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix;
val ie_addr = ie_enc.io.out;
val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
val has_invalid_entry = !tag_cam.io.valid_bits.andR
val invalid_entry = PriorityEncoder(~tag_cam.io.valid_bits)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, repl_count).toUFix;
val lookup = (state === s_ready) && r_cpu_req_val;
val lookup_hit = lookup && tag_hit;
@ -162,7 +159,7 @@ class rocketITLB(entries: Int) extends Component
when (tlb_miss) {
r_refill_tag := lookup_tag;
r_refill_waddr := repl_waddr;
when (!invalid_entry) {
when (!has_invalid_entry) {
repl_count := repl_count + UFix(1);
}
}

6
rocket/src/main/scala/nbdcache.scala
View File

@ -361,10 +361,8 @@ class ReplayUnit extends Component {
val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT)
}
val sdq_val = Reg(resetVal = UFix(0, NSDQ))
val sdq_allocator = new priorityEncoder(NSDQ)
sdq_allocator.io.in := ~sdq_val
val sdq_alloc_id = sdq_allocator.io.out.toUFix
val sdq_val = Reg(resetVal = UFix(0))
val sdq_alloc_id = PriorityEncoder(~sdq_val(NSDQ-1,0))
val replay_val = Reg(resetVal = Bool(false))
val replay_retry = replay_val && !io.data_req.ready

46
rocket/src/main/scala/util.scala
View File

@ -211,46 +211,12 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
dout <> io.out.bits
}
class ioPriorityDecoder(in_width: Int, out_width: Int) extends Bundle
object PriorityEncoder
{
val in = UFix(in_width, INPUT);
val out = Bits(out_width, OUTPUT);
}
class priorityDecoder(width: Int) extends Component
{
val in_width = ceil(log10(width)/log10(2)).toInt;
val io = new ioPriorityEncoder(in_width, width);
val l_out = Wire() { Bits() };
l_out := Bits(0, width);
for (i <- width-1 to 0 by -1) {
when (io.in === UFix(i, in_width)) {
l_out := Bits(1,1) << UFix(i);
}
def apply(in: Bits, n: Int = 0): UFix = {
if (n >= in.getWidth-1)
UFix(n)
else
Mux(in(n), UFix(n), PriorityEncoder(in, n+1))
}
io.out := l_out;
}
class ioPriorityEncoder(in_width: Int, out_width: Int) extends Bundle
{
val in = Bits(in_width, INPUT);
val out = UFix(out_width, OUTPUT);
}
class priorityEncoder(width: Int) extends Component
{
val out_width = ceil(log10(width)/log10(2)).toInt;
val io = new ioPriorityDecoder(width, out_width);
val l_out = Wire() { UFix() };
l_out := UFix(0, out_width);
for (i <- width-1 to 1 by -1) {
when (io.in(i).toBool) {
l_out := UFix(i, out_width);
}
}
io.out := l_out;
}