improve D$ internal interfaces
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28cacd953f
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6d03d75835
@ -94,6 +94,18 @@ class LoadDataGen extends Component {
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io.r_dout_subword := extended_subword
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}
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class MSHRReq extends Bundle {
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val ppn = Bits(width = TAG_BITS)
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val idx = Bits(width = IDX_BITS)
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val way_oh = Bits(width = NWAYS)
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val offset = Bits(width = OFFSET_BITS)
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val cmd = Bits(width = 4)
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val typ = Bits(width = 3)
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val tag = Bits(width = DCACHE_TAG_BITS)
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val data = Bits(width = CPU_DATA_BITS)
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}
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class RPQEntry extends Bundle {
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val offset = Bits(width = OFFSET_BITS)
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val cmd = Bits(width = 4)
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@ -157,14 +169,8 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
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val req_pri_rdy = Bool(OUTPUT)
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val req_sec_val = Bool(INPUT)
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val req_sec_rdy = Bool(OUTPUT)
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val req_ppn = Bits(TAG_BITS, INPUT)
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val req_idx = Bits(IDX_BITS, INPUT)
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val req_offset = Bits(OFFSET_BITS, INPUT)
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val req_cmd = Bits(4, INPUT)
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val req_type = Bits(3, INPUT)
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val req_bits = new MSHRReq().asInput
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val req_sdq_id = UFix(log2up(NSDQ), INPUT)
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val req_tag = Bits(DCACHE_TAG_BITS, INPUT)
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val req_way_oh = Bits(NWAYS, INPUT)
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val idx_match = Bool(OUTPUT)
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val idx = Bits(IDX_BITS, OUTPUT)
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@ -185,39 +191,26 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
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val idx_ = Reg { Bits() }
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val way_oh_ = Reg { Bits() }
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val req_load = (io.req_cmd === M_XRD) || (io.req_cmd === M_PFR)
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val req_use_rpq = (io.req_cmd != M_PFR) && (io.req_cmd != M_PFW)
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val next_state = Mux(io.req_sec_val && io.req_sec_rdy, newStateOnSecondaryMiss(io.req_cmd, state), state)
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val req_cmd = io.req_bits.cmd
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val req_load = (req_cmd === M_XRD) || (req_cmd === M_PFR)
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val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW)
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val next_state = Mux(io.req_sec_val && io.req_sec_rdy, newStateOnSecondaryMiss(req_cmd, state), state)
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val sec_rdy = io.idx_match && !refilled && (needsWriteback(state) || !requested || req_load)
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// XXX why doesn't this work?
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// val rpq = (new queue(NRPQ)) { new RPQEntry() }
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val rpq_enq_bits = Cat(io.req_offset, io.req_cmd, io.req_type, io.req_sdq_id, io.req_tag)
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val rpq = (new queue(NRPQ)) { Bits(width = rpq_enq_bits.getWidth) }
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val rpq = (new queue(NRPQ)) { new RPQEntry }
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
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rpq.io.enq.bits := rpq_enq_bits
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rpq.io.enq.bits := io.req_bits
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rpq.io.enq.bits.sdq_id := io.req_sdq_id
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rpq.io.deq.ready := io.replay.ready && refilled
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var rpq_deq_bits = rpq.io.deq.bits
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io.replay.bits.tag := rpq_deq_bits
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rpq_deq_bits = rpq_deq_bits >> UFix(io.req_tag.width)
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io.replay.bits.sdq_id := rpq_deq_bits.toUFix
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rpq_deq_bits = rpq_deq_bits >> UFix(io.req_sdq_id.width)
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io.replay.bits.typ := rpq_deq_bits
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rpq_deq_bits = rpq_deq_bits >> UFix(io.req_type.width)
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io.replay.bits.cmd := rpq_deq_bits
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rpq_deq_bits = rpq_deq_bits >> UFix(io.req_cmd.width)
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io.replay.bits.offset := rpq_deq_bits
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rpq_deq_bits = rpq_deq_bits >> UFix(io.req_offset.width)
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when (io.req_pri_val && io.req_pri_rdy) {
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valid := Bool(true)
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state := newStateOnPrimaryMiss(io.req_cmd)
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state := newStateOnPrimaryMiss(req_cmd)
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requested := Bool(false)
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refilled := Bool(false)
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ppn := io.req_ppn
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idx_ := io.req_idx
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way_oh_ := io.req_way_oh
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ppn := io.req_bits.ppn
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idx_ := io.req_bits.idx
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way_oh_ := io.req_bits.way_oh
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}
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.otherwise {
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when (io.mem_req.valid && io.mem_req.ready) {
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@ -232,7 +225,7 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
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state := next_state
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}
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io.idx_match := valid && (idx_ === io.req_idx)
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io.idx_match := valid && (idx_ === io.req_bits.idx)
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io.idx := idx_
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io.tag := ppn
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io.way_oh := way_oh_
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@ -253,22 +246,14 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
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io.mem_req.bits.tile_xact_id := Bits(id)
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io.replay.valid := rpq.io.deq.valid && refilled
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io.replay.bits <> rpq.io.deq.bits
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io.replay.bits.idx := idx_
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io.replay.bits.way_oh := way_oh_
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}
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class MSHRFile extends Component {
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val io = new Bundle {
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val req_val = Bool(INPUT)
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val req_rdy = Bool(OUTPUT)
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val req_ppn = Bits(TAG_BITS, INPUT)
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val req_idx = Bits(IDX_BITS, INPUT)
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val req_offset = Bits(OFFSET_BITS, INPUT)
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val req_cmd = Bits(4, INPUT)
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val req_type = Bits(3, INPUT)
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val req_tag = Bits(DCACHE_TAG_BITS, INPUT)
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val req_way_oh = Bits(NWAYS, INPUT)
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val req_data = Bits(CPU_DATA_BITS, INPUT)
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val req = (new ioDecoupled) { new MSHRReq }
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val mem_resp_val = Bool(INPUT)
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val mem_resp_tag = Bits(MEM_TAG_BITS, INPUT)
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@ -288,9 +273,9 @@ class MSHRFile extends Component {
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val sdq_val = Reg(resetVal = Bits(0, NSDQ))
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val sdq_alloc_id = PriorityEncoder(~sdq_val(NSDQ-1,0))
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val sdq_rdy = !sdq_val.andR
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val (req_read, req_write) = cpuCmdToRW(io.req_cmd)
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val sdq_enq = io.req_val && io.req_rdy && req_write
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val sdq = Mem(NSDQ, sdq_enq, sdq_alloc_id, io.req_data)
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val (req_read, req_write) = cpuCmdToRW(io.req.bits.cmd)
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val sdq_enq = io.req.valid && io.req.ready && req_write
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val sdq = Mem(NSDQ, sdq_enq, sdq_alloc_id, io.req.bits.data)
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sdq.setReadLatency(1);
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sdq.setTarget('inst)
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@ -302,7 +287,7 @@ class MSHRFile extends Component {
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val replay_arb = (new Arbiter(NMSHR)) { new Replay() }
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val alloc_arb = (new Arbiter(NMSHR)) { Bool() }
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val tag_match = tag_mux.io.out === io.req_ppn
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val tag_match = tag_mux.io.out === io.req.bits.ppn
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var idx_match = Bool(false)
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var pri_rdy = Bool(false)
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@ -318,15 +303,9 @@ class MSHRFile extends Component {
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alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
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mshr.io.req_pri_val := alloc_arb.io.in(i).ready
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mshr.io.req_sec_val := io.req_val && sdq_rdy && tag_match
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mshr.io.req_ppn := io.req_ppn
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mshr.io.req_tag := io.req_tag
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mshr.io.req_idx := io.req_idx
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mshr.io.req_offset := io.req_offset
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mshr.io.req_cmd := io.req_cmd
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mshr.io.req_type := io.req_type
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mshr.io.req_sec_val := io.req.valid && sdq_rdy && tag_match
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mshr.io.req_bits := io.req.bits
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mshr.io.req_sdq_id := sdq_alloc_id
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mshr.io.req_way_oh := io.req_way_oh
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mshr.io.meta_req <> meta_req_arb.io.in(i)
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mshr.io.mem_req <> mem_req_arb.io.in(i)
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@ -345,12 +324,12 @@ class MSHRFile extends Component {
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idx_match = idx_match || mshr.io.idx_match
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}
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alloc_arb.io.out.ready := io.req_val && sdq_rdy && !idx_match
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alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
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meta_req_arb.io.out <> io.meta_req
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mem_req_arb.io.out <> io.mem_req
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io.req_rdy := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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io.mem_resp_idx := mem_resp_idx_mux.io.out
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io.mem_resp_way_oh := mem_resp_way_oh_mux.io.out
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io.fence_rdy := !fence
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@ -828,22 +807,23 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
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}
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// miss handling
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mshr.io.req_val := tag_miss && r_req_readwrite && (!needs_writeback || wb_rdy)
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mshr.io.req_ppn := cpu_req_tag
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mshr.io.req_idx := r_cpu_req_idx(indexmsb,indexlsb)
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mshr.io.req_tag := r_cpu_req_tag
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mshr.io.req_offset := r_cpu_req_idx(offsetmsb,0)
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mshr.io.req_cmd := r_cpu_req_cmd
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mshr.io.req_type := r_cpu_req_type
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mshr.io.req_way_oh := replaced_way_oh
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mshr.io.req_data := cpu_req_data
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mshr.io.req.valid := tag_miss && r_req_readwrite && (!needs_writeback || wb_rdy)
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mshr.io.req.bits.ppn := cpu_req_tag
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mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
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mshr.io.req.bits.tag := r_cpu_req_tag
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mshr.io.req.bits.offset := r_cpu_req_idx(offsetmsb,0)
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mshr.io.req.bits.cmd := r_cpu_req_cmd
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mshr.io.req.bits.typ := r_cpu_req_type
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mshr.io.req.bits.way_oh := replaced_way_oh
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mshr.io.req.bits.data := cpu_req_data
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mshr.io.mem_resp_val := refill_val && (~rr_count === UFix(0))
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mshr.io.mem_resp_tag := io.mem.xact_rep.bits.tile_xact_id
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mshr.io.mem_req <> wb.io.refill_req
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mshr.io.meta_req <> meta_arb.io.in(1)
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data_arb.io.in(0).bits.inner_req.idx := mshr.io.mem_resp_idx
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data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
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replacer.io.pick_new_way := !io.cpu.req_kill && mshr.io.req_val && mshr.io.req_rdy
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replacer.io.pick_new_way := mshr.io.req.valid && mshr.io.req.ready
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// replays
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val replay = mshr.io.data_req.bits
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@ -904,7 +884,7 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
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val pending_fence = Reg(resetVal = Bool(false))
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pending_fence := (r_cpu_req_val_ && r_req_fence || pending_fence) && !flush_rdy
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val nack_hit = p_store_match || replay_val || r_req_write && !p_store_rdy
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val nack_miss = needs_writeback && !wb_rdy || !mshr.io.req_rdy
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val nack_miss = needs_writeback && !wb_rdy || !mshr.io.req.ready
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val nack_flush = !flush_rdy && (r_req_fence || r_req_flush) ||
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!flushed && r_req_flush
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val nack = early_nack || r_req_readwrite && Mux(tag_match, nack_hit, nack_miss) || nack_flush
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