riscv/rocket-chip
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only instantiate VI$ if HAVE_VEC

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This commit is contained in:
Andrew Waterman 2012-02-21 15:53:19 -08:00
parent c8f768c8b3
commit 9a80adef50
1 changed files with 9 additions and 3 deletions
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12
rocket/src/main/scala/top.scala
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@ -19,16 +19,23 @@ class Top() extends Component {
val cpu = new rocketProc();
val icache = new rocketICache(128, 2); // 128 sets x 2 ways
val icache_pf = new rocketIPrefetcher();
val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
val dcache = new HellaCacheUniproc();
val arbiter = new rocketMemArbiter(4);
arbiter.io.requestor(0) <> dcache.io.mem
arbiter.io.requestor(1) <> icache_pf.io.mem
arbiter.io.requestor(2) <> vicache.io.mem
arbiter.io.requestor(3) <> htif.io.mem
arbiter.io.mem <> io.mem
if (HAVE_VEC)
{
val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
arbiter.io.requestor(2) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu;
}
else
arbiter.io.requestor(2).req_val := Bool(false)
htif.io.host <> io.host
cpu.io.host <> htif.io.cpu(0);
cpu.io.debug <> io.debug;
@ -36,7 +43,6 @@ class Top() extends Component {
icache_pf.io.invalidate := cpu.io.imem.invalidate
icache.io.mem <> icache_pf.io.icache;
cpu.io.imem <> icache.io.cpu;
cpu.io.vimem <> vicache.io.cpu;
cpu.io.dmem <> dcache.io.cpu;
}