add fp writeback arbitration logic
This commit is contained in:
Andrew Waterman
parent
0671a99712
commit
15dc2d8c40
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@ -116,7 +116,7 @@ class rocketProc extends Component
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if (HAVE_FPU)
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{
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val fpu = new rocketFPU
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val fpu = new rocketFPU(4,6)
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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}
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@ -328,6 +328,7 @@ class rocketCtrl extends Component
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val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
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val ex_reg_fp_val = Reg(resetVal = Bool(false));
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val ex_reg_fp_sboard_set = Reg(resetVal = Bool(false));
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val ex_reg_vec_val = Reg(resetVal = Bool(false));
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val ex_reg_replay = Reg(resetVal = Bool(false));
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val ex_reg_load_use = Reg(resetVal = Bool(false));
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@ -349,6 +350,7 @@ class rocketCtrl extends Component
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val mem_reg_replay = Reg(resetVal = Bool(false));
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val mem_reg_kill = Reg(resetVal = Bool(false));
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val mem_reg_ext_mem_val = Reg(resetVal = Bool(false))
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val mem_reg_fp_sboard_set = Reg(resetVal = Bool(false));
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val wb_reg_wen = Reg(resetVal = Bool(false));
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val wb_reg_fp_wen = Reg(resetVal = Bool(false));
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@ -360,6 +362,7 @@ class rocketCtrl extends Component
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val wb_reg_replay = Reg(resetVal = Bool(false));
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val wb_reg_cause = Reg(){UFix()};
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val wb_reg_fp_val = Reg(resetVal = Bool(false));
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val wb_reg_fp_sboard_set = Reg(resetVal = Bool(false));
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val take_pc = Wire() { Bool() };
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@ -402,6 +405,7 @@ class rocketCtrl extends Component
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ex_reg_xcpt_privileged := Bool(false);
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ex_reg_xcpt_syscall := Bool(false);
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ex_reg_fp_val := Bool(false);
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ex_reg_fp_sboard_set := Bool(false);
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ex_reg_vec_val := Bool(false);
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ex_reg_replay := Bool(false);
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ex_reg_load_use := Bool(false);
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@ -424,7 +428,8 @@ class rocketCtrl extends Component
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ex_reg_xcpt_illegal := illegal_inst;
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ex_reg_xcpt_privileged := (id_privileged & ~io.dpath.status(SR_S)).toBool;
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ex_reg_xcpt_syscall := id_syscall.toBool;
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ex_reg_fp_val := io.fpu.dec.valid;
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ex_reg_fp_val := io.fpu.dec.valid
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ex_reg_fp_sboard_set := io.fpu.dec.sboard
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ex_reg_vec_val := id_vec_val.toBool
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ex_reg_replay := id_reg_replay || ex_reg_replay_next;
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ex_reg_load_use := id_load_use;
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@ -473,6 +478,7 @@ class rocketCtrl extends Component
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mem_reg_xcpt_vec := Bool(false);
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mem_reg_xcpt_syscall := Bool(false);
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mem_reg_fp_val := Bool(false);
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mem_reg_fp_sboard_set := Bool(false)
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}
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.otherwise {
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mem_reg_div_mul_val := ex_reg_div_val || ex_reg_mul_val;
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@ -491,6 +497,7 @@ class rocketCtrl extends Component
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mem_reg_xcpt_vec := ex_reg_vec_val && !io.dpath.status(SR_EV).toBool;
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mem_reg_xcpt_syscall := ex_reg_xcpt_syscall;
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mem_reg_fp_val := ex_reg_fp_val
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mem_reg_fp_sboard_set := ex_reg_fp_sboard_set
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}
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mem_reg_ext_mem_val := ex_reg_ext_mem_val;
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mem_reg_mem_cmd := ex_reg_mem_cmd;
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@ -505,6 +512,7 @@ class rocketCtrl extends Component
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wb_reg_flush_inst := Bool(false);
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wb_reg_div_mul_val := Bool(false);
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wb_reg_fp_val := Bool(false)
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wb_reg_fp_sboard_set := Bool(false)
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}
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.otherwise {
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wb_reg_wen := mem_reg_wen;
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@ -515,6 +523,7 @@ class rocketCtrl extends Component
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wb_reg_flush_inst := mem_reg_flush_inst;
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wb_reg_div_mul_val := mem_reg_div_mul_val;
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wb_reg_fp_val := mem_reg_fp_val
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wb_reg_fp_sboard_set := mem_reg_fp_sboard_set
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}
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val sboard = new rocketCtrlSboard(32, 3, 2);
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@ -543,7 +552,7 @@ class rocketCtrl extends Component
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fp_sboard.io.r(2).addr := id_raddr3.toUFix
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fp_sboard.io.r(3).addr := id_waddr.toUFix
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fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen
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fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen || wb_reg_fp_sboard_set
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fp_sboard.io.w(0).data := Bool(true)
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fp_sboard.io.w(0).addr := io.dpath.wb_waddr
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@ -50,14 +50,18 @@ class rocketFPUCtrlSigs extends Bundle
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val cmd = Bits(width = FCMD_WIDTH)
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val valid = Bool()
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val wen = Bool()
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val sboard = Bool()
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val ren1 = Bool()
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val ren2 = Bool()
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val ren3 = Bool()
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val single = Bool()
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val fromint = Bool()
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val toint = Bool()
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val fastpipe = Bool()
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val fma = Bool()
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val store = Bool()
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val fsr = Bool()
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val rdfsr = Bool()
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val wrfsr = Bool()
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}
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class rocketFPUDecoder extends Component
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@ -66,128 +70,68 @@ class rocketFPUDecoder extends Component
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val inst = Bits(32, INPUT)
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val sigs = new rocketFPUCtrlSigs().asOutput
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}
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// val fp =
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// ListLookup(io.dpath.inst,
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// List(FPU_N, FPU_N, FPU_N, FPU_N, FPU_N),
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// Array(
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// FMOVZ -> List(Bool(true)),
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// FMOVN -> List(Bool(true)),
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// FADD_S -> List(Bool(true)),
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// FSUB_S -> List(Bool(true)),
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// FMUL_S -> List(Bool(true)),
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// FDIV_S -> List(Bool(true)),
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// FSQRT_S -> List(Bool(true)),
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// FSGNJ_S -> List(Bool(true)),
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// FSGNJN_S -> List(Bool(true)),
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// FSGNJX_S -> List(Bool(true)),
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// FADD_D -> List(Bool(true)),
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// FSUB_D -> List(Bool(true)),
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// FMUL_D -> List(Bool(true)),
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// FDIV_D -> List(Bool(true)),
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// FSQRT_D -> List(Bool(true)),
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// FSGNJ_D -> List(Bool(true)),
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// FSGNJN_D -> List(Bool(true)),
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// FSGNJX_D -> List(Bool(true)),
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// FCVT_L_S -> List(Bool(true)),
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// FCVT_LU_S -> List(Bool(true)),
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// FCVT_W_S -> List(Bool(true)),
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// FCVT_WU_S -> List(Bool(true)),
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// FCVT_L_D -> List(Bool(true)),
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// FCVT_LU_D -> List(Bool(true)),
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// FCVT_W_D -> List(Bool(true)),
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// FCVT_WU_D -> List(Bool(true)),
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// FCVT_S_L -> List(Bool(true)),
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// FCVT_S_LU -> List(Bool(true)),
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// FCVT_S_W -> List(Bool(true)),
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// FCVT_S_WU -> List(Bool(true)),
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// FCVT_D_L -> List(Bool(true)),
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// FCVT_D_LU -> List(Bool(true)),
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// FCVT_D_W -> List(Bool(true)),
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// FCVT_D_WU -> List(Bool(true)),
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// FCVT_S_D -> List(Bool(true)),
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// FCVT_D_S -> List(Bool(true)),
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// FEQ_S -> List(Bool(true)),
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// FLT_S -> List(Bool(true)),
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// FLE_S -> List(Bool(true)),
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// FEQ_D -> List(Bool(true)),
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// FLT_D -> List(Bool(true)),
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// FLE_D -> List(Bool(true)),
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// FMIN_S -> List(Bool(true)),
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// FMAX_S -> List(Bool(true)),
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// FMIN_D -> List(Bool(true)),
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// FMAX_D -> List(Bool(true)),
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// MFTX_S -> List(Bool(true)),
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// MFTX_D -> List(Bool(true)),
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// MFFSR -> List(Bool(true)),
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// MXTF_S -> List(Bool(true)),
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// MXTF_D -> List(Bool(true)),
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// MTFSR -> List(Bool(true)),
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// FLW -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
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// FLD -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
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// FSW -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N),
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// FSD -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N)
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// FMADD_S -> List(Bool(true)),
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// FMSUB_S -> List(Bool(true)),
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// FNMSUB_S -> List(Bool(true)),
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// FNMADD_S -> List(Bool(true)),
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// FMADD_D -> List(Bool(true)),
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// FMSUB_D -> List(Bool(true)),
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// FNMSUB_D -> List(Bool(true)),
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// FNMADD_D -> List(Bool(true))
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// ));
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val N = Bool(false)
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val Y = Bool(true)
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val X = Bool(false)
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val FCMD_X = FCMD_ADD
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val decoder = ListLookup(io.inst,
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List (N,FCMD_X, X,X,X,X,X,X,X,X,X),
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Array(FLW -> List(Y,FCMD_LOAD, Y,N,N,N,Y,N,N,N,N),
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FLD -> List(Y,FCMD_LOAD, Y,N,N,N,N,N,N,N,N),
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FSW -> List(Y,FCMD_STORE, N,N,Y,N,Y,N,N,Y,N),
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FSD -> List(Y,FCMD_STORE, N,N,Y,N,N,N,N,Y,N),
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MXTF_S -> List(Y,FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N),
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MXTF_D -> List(Y,FCMD_MXTF, Y,N,N,N,N,Y,N,N,N),
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FCVT_S_W -> List(Y,FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N),
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FCVT_D_W -> List(Y,FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N),
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FCVT_S_WU-> List(Y,FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N),
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FCVT_D_WU-> List(Y,FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N),
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FCVT_S_L -> List(Y,FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N),
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FCVT_D_L -> List(Y,FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N),
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FCVT_S_LU-> List(Y,FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N),
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FCVT_D_LU-> List(Y,FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N),
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MFTX_S -> List(Y,FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N),
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MFTX_D -> List(Y,FCMD_MFTX, N,Y,N,N,N,N,Y,N,N),
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FCVT_W_S -> List(Y,FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N),
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FCVT_W_D -> List(Y,FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N),
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FCVT_WU_S-> List(Y,FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N),
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FCVT_WU_D-> List(Y,FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N),
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FCVT_L_S -> List(Y,FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N),
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FCVT_L_D -> List(Y,FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N),
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FCVT_LU_S-> List(Y,FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N),
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FCVT_LU_D-> List(Y,FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N),
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FEQ_S -> List(Y,FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N),
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FEQ_D -> List(Y,FCMD_EQ, N,Y,Y,N,N,N,Y,N,N),
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FLT_S -> List(Y,FCMD_LT, N,Y,Y,N,Y,N,Y,N,N),
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FLT_D -> List(Y,FCMD_LT, N,Y,Y,N,N,N,Y,N,N),
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FLE_S -> List(Y,FCMD_LE, N,Y,Y,N,Y,N,Y,N,N),
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FLE_D -> List(Y,FCMD_LE, N,Y,Y,N,N,N,Y,N,N),
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MTFSR -> List(Y,FCMD_MTFSR, N,N,N,N,Y,Y,Y,N,Y),
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MFFSR -> List(Y,FCMD_MFFSR, N,N,N,N,Y,N,Y,N,Y)
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List (N,FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X),
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Array(FLW -> List(Y,FCMD_LOAD, Y,N,N,N,N,Y,N,N,N,N,N,N,N),
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FLD -> List(Y,FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N,N),
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FSW -> List(Y,FCMD_STORE, N,N,N,Y,N,Y,N,N,N,N,Y,N,N),
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FSD -> List(Y,FCMD_STORE, N,N,N,Y,N,N,N,N,N,N,Y,N,N),
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MXTF_S -> List(Y,FCMD_MXTF, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
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MXTF_D -> List(Y,FCMD_MXTF, Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
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FCVT_S_W -> List(Y,FCMD_CVT_FMT_W, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
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FCVT_S_WU-> List(Y,FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
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FCVT_S_L -> List(Y,FCMD_CVT_FMT_L, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
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FCVT_S_LU-> List(Y,FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
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FCVT_D_W -> List(Y,FCMD_CVT_FMT_W, Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
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FCVT_D_WU-> List(Y,FCMD_CVT_FMT_WU,Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
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FCVT_D_L -> List(Y,FCMD_CVT_FMT_L, Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
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FCVT_D_LU-> List(Y,FCMD_CVT_FMT_LU,Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
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MFTX_S -> List(Y,FCMD_MFTX, N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
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MFTX_D -> List(Y,FCMD_MFTX, N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_W_S -> List(Y,FCMD_CVT_W_FMT, N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
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FCVT_WU_S-> List(Y,FCMD_CVT_WU_FMT,N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
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FCVT_L_S -> List(Y,FCMD_CVT_L_FMT, N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
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FCVT_LU_S-> List(Y,FCMD_CVT_LU_FMT,N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
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FCVT_W_D -> List(Y,FCMD_CVT_W_FMT, N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_WU_D-> List(Y,FCMD_CVT_WU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_L_D -> List(Y,FCMD_CVT_L_FMT, N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_LU_D-> List(Y,FCMD_CVT_LU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FEQ_S -> List(Y,FCMD_EQ, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
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FLT_S -> List(Y,FCMD_LT, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
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FLE_S -> List(Y,FCMD_LE, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
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FEQ_D -> List(Y,FCMD_EQ, N,N,Y,Y,N,N,N,Y,N,N,N,N,N),
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FLT_D -> List(Y,FCMD_LT, N,N,Y,Y,N,N,N,Y,N,N,N,N,N),
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FLE_D -> List(Y,FCMD_LE, N,N,Y,Y,N,N,N,Y,N,N,N,N,N),
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MTFSR -> List(Y,FCMD_MTFSR, N,N,N,N,N,Y,N,Y,N,N,N,Y,Y),
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MFFSR -> List(Y,FCMD_MFFSR, N,N,N,N,N,Y,N,Y,N,N,N,Y,N)
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// FADD_S -> List(Y,FCMD_ADD, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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// FSUB_S -> List(Y,FCMD_SUB, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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// FMUL_S -> List(Y,FCMD_MUL, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
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// FMIN_S -> List(Y,FCMD_MIN, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
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// FMAX_S -> List(Y,FCMD_MAX, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N)
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))
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val valid :: cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: store :: fsr :: Nil = decoder
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val valid :: cmd :: wen :: sboard :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: store :: rdfsr :: wrfsr :: Nil = decoder
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io.sigs.valid := valid.toBool
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io.sigs.cmd := cmd
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io.sigs.wen := wen.toBool
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io.sigs.sboard := sboard.toBool
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io.sigs.ren1 := ren1.toBool
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io.sigs.ren2 := ren2.toBool
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io.sigs.ren3 := ren3.toBool
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io.sigs.single := single.toBool
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io.sigs.fromint := fromint.toBool
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io.sigs.toint := toint.toBool
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io.sigs.fastpipe := fastpipe.toBool
|
||||
io.sigs.fma := fma.toBool
|
||||
io.sigs.store := store.toBool
|
||||
io.sigs.fsr := fsr.toBool
|
||||
io.sigs.rdfsr := rdfsr.toBool
|
||||
io.sigs.wrfsr := wrfsr.toBool
|
||||
}
|
||||
|
||||
class ioDpathFPU extends Bundle {
|
||||
|
|
@ -337,7 +281,7 @@ class rocketIntFPUnit extends Component
|
|||
io.exc := Mux(io.single, exc_s, exc_d)
|
||||
}
|
||||
|
||||
class rocketFPU extends Component
|
||||
class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
|
||||
{
|
||||
val io = new Bundle {
|
||||
val ctrl = new ioCtrlFPU().flip()
|
||||
|
|
@ -390,6 +334,7 @@ class rocketFPU extends Component
|
|||
val fp_fromint_data = Reg() { Bits() }
|
||||
val fp_toint_val = Reg(resetVal = Bool(false))
|
||||
val fp_toint_data = Reg() { Bits() }
|
||||
val fp_wrfsr_val = Reg(resetVal = Bool(false))
|
||||
val fp_cmp_data = Reg() { Bits() }
|
||||
val fp_toint_single = Reg() { Bool() }
|
||||
val fp_toint_cmd = Reg() { Bits() }
|
||||
|
|
@ -397,14 +342,20 @@ class rocketFPU extends Component
|
|||
|
||||
fp_fromint_val := Bool(false)
|
||||
fp_toint_val := Bool(false)
|
||||
fp_wrfsr_val := Bool(false)
|
||||
when (reg_valid) {
|
||||
fp_waddr := reg_inst(31,27)
|
||||
when (ctrl.fromint) {
|
||||
when (ctrl.fromint || ctrl.wrfsr) {
|
||||
fp_fromint_val := !io.ctrl.killx
|
||||
fp_fromint_data := io.dpath.fromint_data
|
||||
}
|
||||
when (ctrl.wrfsr) {
|
||||
fp_wrfsr_val := !io.ctrl.killx
|
||||
}
|
||||
when (ctrl.toint) {
|
||||
fp_toint_val := !io.ctrl.killx
|
||||
}
|
||||
when (ctrl.toint || ctrl.fastpipe) {
|
||||
fp_toint_data := ex_rs1
|
||||
when (ctrl.ren2) {
|
||||
fp_cmp_data := ex_rs2
|
||||
|
|
@ -436,6 +387,7 @@ class rocketFPU extends Component
|
|||
ifpu.io.fsr := Cat(fsr_rm, fsr_exc)
|
||||
ifpu.io.in := fp_fromint_data
|
||||
|
||||
val retire_wrfsr = Reg(!io.ctrl.killm && fp_wrfsr_val, resetVal = Bool(false))
|
||||
val retire_toint = Reg(!io.ctrl.killm && fp_toint_val, resetVal = Bool(false))
|
||||
val retire_toint_exc = Reg(fpiu.io.exc)
|
||||
val retire_fromint = Reg(!io.ctrl.killm && fp_fromint_val, resetVal = Bool(false))
|
||||
|
|
@ -448,18 +400,57 @@ class rocketFPU extends Component
|
|||
Fill(fsr_exc.getWidth, retire_toint) & retire_toint_exc |
|
||||
Fill(fsr_exc.getWidth, retire_fromint) & retire_fromint_exc
|
||||
}
|
||||
when (retire_toint && retire_fromint) { // MTFSR
|
||||
when (retire_wrfsr) { // MTFSR
|
||||
fsr_exc := retire_fromint_wdata(4,0)
|
||||
fsr_rm := retire_fromint_wdata(7,5)
|
||||
}
|
||||
|
||||
regfile.write(retire_fromint_waddr, retire_fromint_wdata, retire_fromint && !retire_toint)
|
||||
// writeback arbitration
|
||||
val wen = Reg(resetVal = Bits(0, dfma_latency-1))
|
||||
val winfo = Vec(dfma_latency-1) { Reg() { Bits() } }
|
||||
val mem_stage_wen = Reg(resetVal = Bool(false))
|
||||
|
||||
val fp_inflight = fp_toint_val || retire_toint || fp_fromint_val || retire_fromint
|
||||
val mtfsr_inflight = fp_toint_val && fp_fromint_val || retire_toint && retire_fromint
|
||||
val fsr_busy = ctrl.fsr && fp_inflight || mtfsr_inflight
|
||||
val fastpipe_latency = 2
|
||||
require(fastpipe_latency < sfma_latency && sfma_latency <= dfma_latency)
|
||||
val ex_stage_fu_latency = Mux(ctrl.fastpipe, UFix(fastpipe_latency-1),
|
||||
Mux(ctrl.single, UFix(sfma_latency-1),
|
||||
UFix(dfma_latency-1)))
|
||||
val mem_stage_fu_latency = Reg(ex_stage_fu_latency - UFix(1))
|
||||
val write_port_busy = ctrl.fastpipe && wen(fastpipe_latency-1) ||
|
||||
Bool(sfma_latency < dfma_latency) && ctrl.fma && ctrl.single && wen(sfma_latency-1) ||
|
||||
mem_stage_wen && mem_stage_fu_latency === ex_stage_fu_latency
|
||||
mem_stage_wen := reg_valid && !io.ctrl.killx && (ctrl.fma || ctrl.fastpipe)
|
||||
val ex_stage_wsrc = Cat(ctrl.fastpipe, ctrl.single)
|
||||
val mem_stage_winfo = Reg(Cat(reg_inst(31,27), ex_stage_wsrc))
|
||||
|
||||
for (i <- 0 until dfma_latency-2) {
|
||||
winfo(i) := winfo(i+1)
|
||||
}
|
||||
when (mem_stage_wen) {
|
||||
when (!io.ctrl.killm) {
|
||||
wen := (wen >> UFix(1)) | (UFix(1) << mem_stage_fu_latency)
|
||||
}
|
||||
for (i <- 0 until dfma_latency-1) {
|
||||
when (UFix(i) === mem_stage_fu_latency) {
|
||||
winfo(i) := mem_stage_winfo
|
||||
}
|
||||
}
|
||||
}
|
||||
.otherwise {
|
||||
wen := wen >> UFix(1)
|
||||
}
|
||||
|
||||
val wsrc = winfo(0)(1,0)
|
||||
val wdata = Mux(wsrc === UFix(0), UFix(0), // DFMA
|
||||
Mux(wsrc === UFix(1), UFix(0), // SFMA
|
||||
Mux(wsrc === UFix(2), retire_fromint_wdata,
|
||||
retire_fromint_wdata)))
|
||||
val waddr = winfo(0) >> UFix(2)
|
||||
regfile.write(waddr, wdata, wen(0))
|
||||
|
||||
val fp_inflight = fp_toint_val || retire_toint || mem_stage_wen || wen.orR
|
||||
val fsr_busy = ctrl.rdfsr && fp_inflight || fp_wrfsr_val || retire_wrfsr
|
||||
val units_busy = Bool(false)
|
||||
val write_port_busy = Bool(false)
|
||||
io.ctrl.nack := fsr_busy || units_busy || write_port_busy
|
||||
io.ctrl.dec <> fp_decoder.io.sigs
|
||||
// we don't currently support round-max-magnitude (rm=4)
|
||||
|
|
|
|||
Loading…
Reference in New Issue